Texas Instruments CDCM61001, Руководство пользователя

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Output Buffer Termination
NOTE: A bypassed output (same as the reference clock frequency) is only available with LVPECL
outputs.
6.4 Using ENABLE and RSTN Pins
JP22 (CHIP-DISABLE) is the jumper for the CE pin. This pin has an internal, 150-k Ω , pull-up resistor; it is
recommended to use the internal pull-up resistor only for logic '1'.
Table 5 summarizes the power-down configuration.
Table 5. Power-Down Configuration
Control Input
CE Operating Condition Output
0 Power Down Hi-Z
1 Normal Active
Do not connect this jumper for normal operation.
The RSTN pin is connected to both CHIP_RESET jumper JP21 and pushbutton switch RESET1. Either
option can be used to reset the device (including recalibrating the PLL). If any settings change on either
the PR0 or the PR1 pins, PLL recalibration is required to generate the proper VCO frequency.
Table 6 lists the RESET configuration options.
Table 6. Reset Configuration
Control Input
RSTN Operating Condition Output
0 Device Reset Hi-Z
0
→
1 PLL Recalibration Hi-Z
1 Normal Active
7 Output Buffer Termination
This EVM is designed to support proper termination for all three types of output buffers. Proper
components must be selected or placed to make sure the chosen output buffer works properly with the
correct termination as expected.
Figure 4 shows different ways to terminate the outputs of the device.
Figure 4. EVM Output Termination Options
7.1 Output Buffer Examples
LVPECLOutput Buffer: Jumpers J24 and J26 should be used. This connection is illustrated in Figure 5 .
5 SCAU027B – March 2009 – Revised March 2011 Low Phase Noise Clock Evaluation Module
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