ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
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SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
(1)
,
Figure 17
and
Figure 18
)
PARAMETER
TEST CONDITIONS
PMMCOREVx
V
CC
MIN
TYP
MAX
UNIT
1.8 V
11
0
ns
3.0 V
8
t
STE,LEAD
STE lead time, STE low to clock
2.4 V
7
3
3.0 V
6
1.8 V
3
0
ns
3.0 V
3
STE lag time, Last clock to STE
t
STE,LAG
high
2.4 V
3
3
3.0 V
3
1.8 V
66
0
ns
3.0 V
50
STE access time, STE low to
t
STE,ACC
SOMI data out
2.4 V
36
3
3.0 V
30
1.8 V
30
0
ns
3.0 V
23
STE disable time, STE high to
t
STE,DIS
SOMI high impedance
2.4 V
16
3
3.0 V
13
1.8 V
5
0
ns
3.0 V
5
t
SU,SI
SIMO input data setup time
2.4 V
2
3
ns
3.0 V
2
1.8 V
5
0
ns
3.0 V
5
t
HD,SI
SIMO input data hold time
2.4 V
5
3
ns
3.0 V
5
1.8 V
76
0
ns
3.0 V
60
UCLK edge to SOMI valid,
t
VALID,SO
SOMI output data valid time
(2)
C
L
= 20 pF
2.4 V
44
3
ns
3.0 V
40
1.8 V
18
0
ns
3.0 V
12
t
HD,SO
SOMI output data hold time
(3)
C
L
= 20 pF
2.4 V
10
3
ns
3.0 V
8
(1)
f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥
max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
see the SPI parameters of the attached master.
(2)
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in
Figure 15
and
Figure 16
.
(3)
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in
Figure 15
and
Figure 16
.
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