34
SWRS224A – FEBRUARY 2019 – REVISED AUGUST 2019
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Terminal Configuration and Functions
Copyright © 2019, Texas Instruments Incorporated
Table 4-3. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
DESCRIPTION
UART
UART1_TX
3
I/O
O
UART TX data
7
I/O
O
12
I/O
O
46
I/O
O
48
I/O
O
UART1 TX data
UART1_RX
4
I/O
I
UART RX data
8
I/O
I
18
I/O
I
47
I/O
I
UART1 RX data
49
I/O
I
UART1_RTS
44
I/O
O
UART1 request-to-send (active low)
52
I/O
O
UART1_CTS
51
I/O
I
UART1 clear-to-send (active low)
UART0_TX
9
I/O
O
UART0 TX data
42
I/O
O
46
I/O
O
52
I/O
O
UART0_RX
10
I/O
I
UART0 RX data
47
I/O
I
UART0 RX data
UART0_CTS
44
I/O
I
UART0 clear-to-send input (active low)
51
UART0_RTS
44
I/O
O
UART0 request-to-send (active low)
51
I/O
O
52
I/O
O
Sense-On-
Power
SOP2
O
I
Sense-on-power 2
SOP1
24
I
I
Configuration sense-on-power 1
SOP0
34
I
I
Configuration sense-on-power 0
(1) LPDS retention unavailable.
(2) The CC3235MOD modules are compatible with TI BLE modules using an external RF switch.
(3) Future support.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
