Table 9-4. Memory Map (continued)
START ADDRESS
END ADDRESS
DESCRIPTION
COMMENT
0xE004 0000
0xE004 0FFF
Trace port interface unit (TPIU)
0xE004 1000
0xE004 1FFF
Reserved for embedded trace macrocell (ETM)
0xE004 2000
0xE00F FFFF
Reserved
(1)
Additional memory is available in the CC3220SF device (not available in CC3200R device).
9.8 Restoring Factory Default Configuration
The module has an internal recovery mechanism that rolls back the file system to its predefined factory image
or restoring the factory default parameters of the device. The factory image is kept in a separate sector on the
sFLASH in a secure manner and cannot be accessed from the host processor. The following restore modes are
supported:
• None—no factory restore settings
• Enable restore of factory default parameters
• Enable restore of factory image and factory default parameters
The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins and
toggling the nRESET pin from low to high.
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial Flash vendor.
9.9 Boot Modes
9.9.1 Boot Mode List
The CC3220MODx and CC3220MODAx module implements a sense-on-power (SoP) scheme to determine the
device operation mode.
SoP values are sensed from the module pin during power up. This encoding determines the boot flow. Before
the device is taken out of reset, the SoP values are copied to a register and used to determine the device
operation mode while powering up. These values determine the boot flow as well as the default mapping for
some of the pins (JTAG, SWD, UART0).
lists the pull configurations.
All CC3220MODx and CC3220MODAx modules contain internal pull down resistors on the SOP[2:0] lines. The
application can use SOP2 for other functions after chip has powered up. However, to avoid spurious SOP values
from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The SOP0
and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.
Table 9-5. CC3220MODx and CC3220MODAx Functional Configurations
NAME
SOP[2]
SOP[1]
SOP[0]
SoP MODE
COMMENT
UARTLOAD
Pullup
Pulldown
Pulldown
LDfrUART
Factory, lab Flash, and SRAM loads
through the UART. The device waits
indefinitely for the UART to load code.
The SOP bits then must be toggled to
configure the device in functional mode.
Also puts JTAG in 4-wire mode.
FUNCTIONAL_2WJ
Pulldown
Pulldown
Pullup
Fn2WJ
Functional development mode. In this
mode, 2-pin SWD is available to the
developer. TMS and TCK are available
for debugger connection.
FUNCTIONAL_4WJ
Pulldown
Pulldown
Pulldown
Fn4WJ
Functional development mode. In this
mode, 4-pin JTAG is available to the
developer. TDI, TMS, TCK, and TDO are
available for debugger connection. The
default configuration for CC3220MODx
and CC3220MODAx modules.
SWRS206E – MARCH 2017 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
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