Texas Instruments CC2500, Руководство пользователя

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CC2500
SWRS040C Page 21 of 89
Figure 6: SmartRF

Studio [5] User Interface
10 4-wire Serial Configuration and Data Interface
CC2500
is configured via a simple 4-wire SPI-
compatible interface (
SI
,
SO
,
SCLK
and
CSn
)
where
CC2500
is the slave. This interface is
also used to read and write buffered data. All
transfers on the SPI interface are done most
significant bit first.
All transactions on the SPI interface start with
a header byte containing a R/W bit, a burst
access bit (B), and a 6-bit address (A
5
– A
0
).
The
CSn
pin must be kept low during transfers
on the SPI bus. If
CSn
goes high during the
transfer of a header byte or during read/write
from/to a register,
the transfer will be
cancelled. The timing for the address and data
transfer on the SPI interface is shown in
Figure 7 with reference to Table 16.
When
CSn
is pulled low, the MCU must wait
until
CC2500
SO
pin goes low before starting to
transfer the header byte. This indicates that
the crystal is running. Unless the chip was in
the SLEEP or XOFF states, the
SO
pin will
always go low immediately after taking
CSn
low.