PCLK
PDI
PSEL
Address
Write mode
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data byte
T
HD
T
SS
T
CL,min
T
CH,min
T
HS
W
T
SD
PDO
SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
5.5
4-wire Serial Configuration Interface
CC1020 is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and PSEL) where
CC1020 is the slave. There are 8-bit configuration registers, each addressed by a 7-bit address. A
Read/Write bit initiates a read or write operation. A full configuration of CC1020 requires sending 33 data
frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration
depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less
than 53 ms. Setting the device in power down mode requires sending one frame only and will in this case
take less than 2 ms. All registers are also readable.
During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data
frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the
first bit. The next bit is the R/W bit (high for write, low for read). The 8 data-bits are then transferred
(D7:0). During address and data transfer the PSEL (Program Select) must be kept low. See
The timing for the programming is also shown in
with reference to
. The clocking of
the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of
PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is
loaded into the internal configuration register.
The configuration data will be retained during a programmed power down mode, but not when the power
supply is turned off. The registers can be programmed in any order.
The configuration registers can also be read by the microcontroller via the same configuration interface.
The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. CC1020 then
returns the data from the addressed register. PDO is used as the data output and must be configured as
an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be sampled at
the positive edge. The read operation is illustrated in
.
PSEL must be set high between each read/write operation.
Figure 5-4. Configuration Registers Write Operation
20
Detailed Description
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links:
