bq77915EVM Quick-Start Guide
5
SLUUBU2B – March 2018 – Revised August 2018
Copyright © 2018, Texas Instruments Incorporated
bq77915 3-5S Low Power Protector Evaluation Module
•
Supply terminal block (J2)
These are the supply terminals for the board. BATT+ or CELL5 is the positive terminal of the power
supply and BATT– is the negative terminal of the power supply. The inputs CELL1 through CELL4 are
divided between the BATT+ and BATT– voltages. When using a power supply for evaluation, be sure
the power supply can accept or is protected from any reverse current such as with a blocking diode if
another supply is used in the system.
•
Pack terminals (J9)
PACK+ and PACK– terminals are for attachment for the load or charger. If using a power supply to
simulate a charger, be sure it can accept or is protected from any reverse current.
•
Shunts on J3
Shunts should be placed shorting J3 pins 1 to 2 and pins 3 to 4. The shunt on pins 1 and 2 connects
the IC VTB pin to the temperature measurement path. A hot temperature is simulated when the shunt
on pins 1 to 2 is removed. The shunt on pins 3 and 4 connects the IC TS pin to the thermistor. A cold
temperature is simulated when the shunt is removed.
•
Shunt on J4
A shunt should be placed shorting J4 pins 2 to 3. The shunt pulls up the IC PRES pin to wake the IC.
Remove the shunt to allow the part to hibernate.
•
Shunt on J5
A shunt should be placed shorting J5 pins 1 to 2. The shunt pulls down the IC CBI pin to enable cell
balancing. Remove the shunt to disable cell balancing.
•
Shunt on J6
A shunt should be placed shorting J6 pins 13 to 14. The 100-k
Ω
OCDP resistor connected by the
shunt selects the EEPROM defined OCD delays. See
bq77915 3-5S Low Power Protector with Cell
for a description of OCDP options.
2.4
Quick-Start Sequence
These steps describe a simple demonstration or check of the operation of the bq77915EVM in a 5S
configuration with a typical 18-V stack voltage.
1. Connect five 200-
Ω
resistors between the cell terminals of J3.
2. Confirm that shunts are in place on J3 shorting pins 1 to 2 and 3 to 4.
3. Confirm a shunt is in place on the J4 pins 2 to 3 to enable the IC.
4. Confirm a shunt is in place on the J5 pins 1 to 2 to enable balancing.
5. Confirm a shunt is in place on the J6 pins 13 to 14 to select the EEPROM-defined OCD delays.
6. Connect an 18-V adjustable DC power supply across the BATT+ and BATT– terminals of J3.
7. Enable the supply.
8. Measure the voltage on the pack terminals. Observe that this is the same voltage as the supply
because both charge and discharge FETs are on, approximately 18 V.
9. Connect a load such as a 5-k
Ω
resistor across the PACK terminals
10. Adjust the supply voltage to 22 V to simulate an overvoltage condition. Observe that the voltage on
the PACK terminals is approximately 600 mV below the supply voltage because the charge FET is off.
11. Adjust the supply voltage to 18 V to cause recovery from the overvoltage condition. Observe that the
voltage on the PACK terminals is the supply voltage.
12. Remove the shunt on pins 1-2 of J4 to simulate a hot condition. Observe that the pack voltage drops
to approximately 0 V, and returns to normal when the shunt is re-installed.
13. Remove the shunt on pins 3-4 of J4 to simulate a cold condition. Observe that the pack voltage drops
to approximately 0 V and returns to normal when the shunt is re-installed.
14. Adjust the supply voltage to 12 V to simulate an undervoltage condition. Observe that the pack
voltage drops to approximately 0 V.
15. Adjust the supply voltage to 18 V to allow recovery from the undervoltage condition. Observe that the
pack voltage remains at approximately 0 V with the load resistor in place.
