Additional Evaluation Setups
10
SLUUBU2B – March 2018 – Revised August 2018
Copyright © 2018, Texas Instruments Incorporated
bq77915 3-5S Low Power Protector Evaluation Module
3.5
Troubleshooting
If the bq77915 does not appear to be operating, check the VDD voltage at TP1 as this should be the
same as the BATT+ voltage. Check that the shunt is installed at J4 pins 2 to 3 to exit hibernate mode.
Check the AVDD voltage at J8 pin 3, this should be approximately 2.5 V. Check that the shunts are
installed on J3 shorting pins 1 to 2 and pins 3 to 4. Check that the cell input voltages are within the
operating range of the part. If a fault has been induced, check that the recovery condition has been met.
The configuration of the supplied IC requires load removal for recovery from undervoltage; therefore,
remove any load from the PACK terminals or supply a charge voltage to recover from UV after the cell
voltages have returned to normal. The
section is a good procedure to check the basic
operation of the board. If the board has been used for stacking evaluation be sure the R7 and R8 resistors
have been replaced.
3.6
Changing Configuration or Conditions
If the board is modified to change the IC or other components or is operated at an expanded temperature
range, be sure to check component temperatures and other operating characteristics to be sure the board
does not provide a hazard in evaluation. A sample IC device may allow more current flow with higher
surface temperatures. Alternate FETs may require a change to the gate resistor to provide an appropriate
switching time.
4
bq77915EVM Optional Circuit Features
This section contains information on other EVM features.
4.1
Alternate FETs
The EVM has TO-220 footprints for use as test points or power FETs as options for evaluation.
4.2
Single-Ended Filter Capacitors
C2, C4, C5, and C7 are patterns for single-ended filters on the battery input terminals, if desired. With the
internal cell balancing, differential capacitors may be preferred, they distribute voltages during cell
connection and avoid conduction of the internal balance FET body diodes. VC1 should use a single-ended
capacitor to avoid pushing VC0 below VSS during load transients.
4.3
Other Uninstalled Components
The bq77915 EVM contains patterns for the stacking interface. Refer to
and
for
additional information.
4.4
Cell Balance Indicators
The bq77915 EVM contains LED indicators with current-limit resistors in parallel with the input filter
resistors. These indicators are not typically part of a battery circuit but are provided for evaluation. The
indicators will glow dimly when balancing with a low-impedance source. When operated with a resistor cell
simulator, the indicators will not typically illuminate since the resistor voltage will drop when balancing
turns on. To see the indicator, enable balancing with the J5 shunt, apply a supply voltage across the cell
and raise its voltage above the other cells and the balancing or OV threshold. Do not increase the cell
voltage significantly beyond OV to make the indicator brighter since higher balancing current into the
bq77915 may exceed the absolute maximum rating.
4.5
OCD Timing
The EVM supports changing the overcurrent protection delay by moving the jumper on J6 to select
different resistor values for the OCDP pin. See
bq77915 3-5S Low Power Protector with Cell Balancing
for details and the EVM schematic (
) for supported resistors.
