Texas Instruments BQ25720, Руководство пользователя, Страница: 3 / 24

Table 1-1 lists the I/O descriptions.
Table 1-1. I/O Description
Jack Description
J1–VIN Input: positive terminal
J1–PGND Input: negative terminal (ground terminal)
J2-ILIM_HIZ External converter disable
J2-CHRG_OK CHRG_OK output
J2-ENZ_OTG External OTG disable pin
J2-CELL_control External battery removal control; logic high to pull the CELL pin down
J3–3V3 Onboard 3.3-V output
J3–SDA SMBUS or I
2
C SDA
J3-SCL SMBUS or I
2
C SCL
J3-GND Ground
J4-CMPOUT CMPOUT pin output
J4-GND Ground
J4-CMPIN External CMPIN pin input
J5-VBAT Connected to battery pack output
J5-PGND Ground
J6-VSYS Connected to system output
J6-PGND Ground
J7–SDA
SMBUS or I
2
C SDA
J7-SCL SMBUS or I
2
C SCL
J7-GND Ground
Table 1-2 displays the controls and key parameters settings.
Table 1-2. Controls and Key Parameters Setting
Jumper Description Factory Setting
JP1 Bypass inrush control circuit
spa. JP1 on: bypasses input FETs Q6 and Q7 external selector
spa. JP1 off: CHRG_OK controls Q6 and Q7 external selector
Installed
JP2 Jumper on: Forward Mode
Jumper off: OTG Mode Installed
JP3 CELL setting:
spa 1S: JP3(1-2), measure CELL pin voltage 1.5 V
spa 2S: JP3(3-4), measure CELL pin voltage 2.4 V
spa 3S: JP3(5-6), measure CELL pin voltage 3.3 V
spa 4S: JP3(7-8), measure CELL pin voltage 4.5 V
2S setting: JP3(3-4)
JP4 Jumper on: Bat removal Jumper off: Cell setting by JP3 Not installed
JP6 For input current setting:
spa Jumper on: ILIM_HIZ LOW.
spa Jumper off: Allow pre-bias ILIM_HIZ
Not installed
JP7 VBUS source selection
spa. JP7 (1-2): VBUS pin on V
IN
spa. JP7 (2-3): VBUS pin on ACP
Installed: JP7(1-2)
JP8 Jumper on: Onboard LDO to drive the EVM 3V3
Jumper off: disconnect onboard LDO to drive the EVM 3V3 Installed
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SLUUC74 – MAY 2021
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