PCB Layout Guideline
7
SLUUBK9 – September 2017
Copyright © 2017, Texas Instruments Incorporated
bq25600, bq25600D PWR771 Evaluation Module
2.3.5
Helpful Tips
•
The leads and cables to the various power supplies, batteries and loads have resistance. The current
meters also have series resistance. The charger dynamically reduces charge current depending on the
voltage sensed at its VBUS pin (using the VINDPM feature), BAT pin (as part of normal termination),
and TS pin (through its battery temperature monitoring feature via battery thermistor). Therefore,
voltmeters must be used to measure the voltage as close to the IC pins as possible instead of relying
on the digital readouts of the power supply. If a battery thermistor is not available, make sure shunts
JP9 and JP10 are in place.
•
When using a source meter that can source and sink current as your battery simulator, TI highly
recommends adding a large (1000+
μ
F) capacitor at the EVM BAT and GND connectors in order to
prevent oscillations at the BAT pin due to mismatched impedances of the charger output and source
meter input within their respective regulation loop bandwidths. Configuring the source meter for 4-wire
sensing eliminates the need for a separate voltmeter to measure the voltage at the BAT pin. When
using 4-wire sensing, always ensure that the sensing leads are connected in order to prevent
accidental overvoltage by the power leads.
•
For precise measurements of charge current and battery regulation near termination, the current meter
in series with the battery or battery simulator should not be set to auto-range and may need be
removed entirely. An alternate method for measuring charge current is to either use an oscilloscope
with hall effect current probe or place a 1% or better, thermally capable (for example, 0.010
Ω
in 1210
or larger footprint) resistor in series between the BAT pin and battery and measure the voltage across
that resistor.
3
PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID pin and GND pin connections and use the
shortest copper trace connection or GND plane.
2. Put an output capacitor near to the inductor and the IC.
3. Decoupling capacitors should be placed next to the IC pins and make the trace connection as short as
possible.
4. Place the inductor input terminal and SW pin as close as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace is wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
5. It is OK to connect all grounds together to reduce PCB size and improve thermal dissipation.
6. Try to avoid ground planes in parallel with high frequency traces in other layers
See the EVM design for the recommended component placement with trace and via locations.
4
Board Layout, Schematic, and Bill of Materials
4.1
Schematic
shows the schematic for the bq25600 EVM.
