Texas Instruments BOOST-PSEMTHR-007, Руководство пользователя, Страница: 21 / 38

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EVM Schematic, Layout Guidelines, PCB Assembly and Layer Plots
21 SLVUBP0A – May 2019 – Revised August 2019
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TPS23881EVM: PoE, PSE, TPS23881 Evaluation Module
6.2 Layout Guidelines
6.2.1 Supply Voltage Decoupling
Provide power supply pin bypass to the TPS23881 device as follows:
• 0.1 µF, 100 V, X7R ceramic at pin 28 (VPWR)
• 0.1 µF, 50 V, X7R ceramic at pin 1 (VDD)
6.2.2 Port Current Kelvin Sensing
KSENSA is shared between SEN1 and SEN2, while KSENSB is shared between SEN3 and SEN4. In
order to optimize the accuracy of the measurement, the PCB layout must be done carefully to minimize
the impact of PCB trace resistance. Refer to
Figure 21 as an example.
6.2.3 Ground Plane Spacing and Isolation (GND, GND1, and EARTH Nets)
Appropriate spacing should be provided between the GND, GND1, and EARTH nets as shown in
Figure 17 .
6.3 PCB Drawings
Figure 15 through Figure 23 show the PCB layouts and assemblies for this EVM.
Figure 15. BOOST-PSEMTHR-007 (Motherboard) Top Side Assembly