Other Custom Configurations
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Note:
1.The sum of C1 and C2 comprises the valid signature capacitance. In practice, this configuration can delete C2 and
change C1 to 0.1µF.
2. R6 may need to be installed for classification other than the default Class 0. Refer to LM5073 datasheet for R6
selection.
3. The installed R7 (15.8k) is intended for high power PD applications, which sets the dc current limit to 800 mA. For
fully compliant applications, R7 may need to be removed or replaced in order to limit the dc current per IEEE 802.3af.
Refer to LM5073 datasheet for R7 selection.
Figure 5. Non Isolated PD Implementation with LM5576 Buck Regulator
13
Other Custom Configurations
The evaluation board also includes the following additional features. For circuit details refer to the
complete schematic in the last section of this article.
•
An LED to indicate the PoE operation mode. This feature is selected by shorting JMP7. The bias
voltage Vcc referenced to GND node from the DC-DC converter is required to feed into P13. Note that
the Vcc voltage shall not exceed 14V.
•
A low cost circuit to produce the startup bias voltage for the DC-DC converter’s controller. It is required
when the RAUX input voltage is not adequate for the controller to start. To select this feature, install
D3 and R25 according to
Table 7
, and have JMP2’s pins 2 and 3 shorted but pin 1 open.
•
A linear regulator to produce the startup bias voltage for the DC-DC converter’s controller when the
RAUX input voltage varies over a wide range from under 14V to above 14V. To select this feature,
install D6, Q1, R13, R14, Z3 according to the
Table 7
, and have JMP2’s pins 1 and 2 shorted but pin 3
open.
•
An efficient MOSFET inrush limiter for the RAUX input line. It is to replace the lossy resistor limiter of
R17 and R18. To select this feature, install C7, Q2, R14, R15, R16, Z3 according to
Table 7
, and have
JMP3’s pins 1 and 2 shorted but pin 3 open.
•
External pull up of the SD and nSD pins. The bias voltage Vcc referenced to GND node from the DC-
DC converter is required to feed into P13. To pull up the nSD pin, short JMP8’s pins 1 and 2; to pull up
the SD pin, short JMP8’s pins 2 and 3. Note that the Vcc voltage shall not exceed 14V. If the Vcc
voltage is greater than 14V, R28 and R29 shall be installed to reduce the voltage applied to the SD
and nSD pins.
•
An input common mode filter. To select this feature, install T1, C9 and C10 according to
Table 7
, and
8
AN-1574 LM5073 Evaluation Board
SNVA214A – April 2007 – Revised April 2013
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