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Configuration 2: 802.3af Fully Compliant PD Interface with Front Aux Power Support
Note:
1.The sum of C1 and C2 comprises the valid signature capacitance. In practice, this configuration can delete C2 and
change C1 to 0.1µF.
2. R6 may need to be installed for classification other than the default Class 0. Refer to LM5073 datasheet for R6
selection.
3. The installed R7 (15.8k) is intended for high power PD applications, which sets the dc current limit to 800 mA. For
fully compliant applications, R7 may need to be removed or replaced in order to limit the dc current per IEEE 802.3af.
Refer to LM5073 datasheet for R7 selection.
Figure 2. IEEE 802.3af Fully Compliant PD Interface
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Configuration 2: 802.3af Fully Compliant PD Interface with Front Aux Power Support
Figure 3
shows the evaluation board configuration for an IEEE 802.3af fully compliant PD interface with
front Aux power support. In order to obtain IEEE 802.3af specified maximum power, the Aux source
voltage should be greater than 20V. Otherwise the obtainable power from the Aux source will be limited by
the LM5073’s maximum current limit of 800 mA. For higher power PD applications, the Aux source voltage
applicable to the FAUX input depends on the power level, conversion efficiency, and the 800mA limit.
Note that R11 (24.9k) is used to overcome any leakage current of D1 and avoid faulty FAUX pin potential
during PoE operation when the FAUX source is absent.
The following table shows the jumper positions for this configuration.
Table 3. Jumper Positions of Configuration 2
Jumper
Function
JMP4, JMP5
Pins 2 and 3 short, Pin 1 open.
JMP6
Pins 2 and 3 short, Pin 1 open.
JMP7
Pins open.
JMP8
All three pins open.
Jumper pins short when the on-board buck regulator is used.
JMP9, JMP11, JMP12, JMP13
Jumper pins open when an external dc-dc converter is used.
Other Jumpers
Not relevant.
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SNVA214A – April 2007 – Revised April 2013
AN-1574 LM5073 Evaluation Board
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