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Aux Power Up Sequence
Full Power Application
The PSE enters full power application mode after Classification. Before the PoE input voltage reaches the
UVLO release threshold, the hot swap MOSFET is in the OFF state. Thus, all circuits referenced to the
GND node remain at high potential. The voltage across the hot swap MOSFET, namely the voltage
between the RTN and VEE pins, will be approximately equal to the PoE input voltage seen across the VIN
and VEE pins.
The evaluation board uses the default UVLO setting of the LM5073 by shorting the UVLO and VIN pins.
To program UVLO thresholds to different values, refer to the LM5073 datasheet for the selection of C3,
R1, R2 and R3.
When the PoE input voltage reaches the UVLO release threshold, the UVLO is released. The hot swap
MOSFET is turned on, and the PD interface enters the inrush limiting mode. The limited inrush current
charges up the DC-DC converter’s input capacitors.
Power Good Establishment and Startup of the DC-DC Converter
As the DC-DC converter’s input capacitors are charging up, the potential of the RTN is decreasing with
respect to the VEE pin potential. Once the RTN pin potential drops below 1.5V (referenced to VEE), power
good is asserted by pulling the nPGOOD pin low, and the SD and nSD pins establish the normal states to
turn on the DC-DC converter. Then, the DC-DC converter will enter the soft start mode. After the soft start
is complete, the DC-DC converter enters steady state operation and output regulation will be achieved.
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Aux Power Up Sequence
The FAUX input power up sequence is similar to that of the PoE input, with the exception that the UVLO
release threshold is overridden when the FAUX pin is pulled up.
The RAUX input power up sequence is simpler:
•
RAUX power application quickly charges the input capacitors. The RAUX input inrush limit resistors
limit the inrush current and prevent any overshoot of the voltage between the VIN and RTN pins.
•
The hot swap MOSFET is turned off, the DC-DC converter’s input capacitors are charged up,, and the
SD and nSD pins establish the normal states to turn on the DC-DC converter.
•
The DC-DC converter will enter the soft start mode. After the soft start is complete, the DC-DC
converter enters steady state operation and the output regulation will be achieved.
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Performance Characteristics
Figure 6
shows key waveforms during a normal PoE power up sequence. Please note that the PSE used
in the test goes through detection mode, but does not perform classification and directly enters full power
application mode.
Horizontal Resolution: 50 ms/div.
Trace 1: PoE input voltage across the VIN and VEE pins. 20V/div.
Trace 2: Voltage across the RTN and VEE pins, namely the voltage across the Hot Swap MOSFET. 20V/div.
Trace 3: The input current. 0.2A/div.
Trace 4: The 3.3V output voltage. 2V/div.
Figure 6. PoE Power Up Sequence with a Midspan PSE
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SNVA214A – April 2007 – Revised April 2013
AN-1574 LM5073 Evaluation Board
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