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Schematic

3-7

Schematic and Layout

3.2

Schematic

Figure 3−6.

ADSDeSer-50EVM

—Schematic

tle

Num

Dat

hee

Fil

e:C

:\D

ett

ing

s\.

.\8

liz

CHD

By:

IO _L9

6 N_

1 /G

C LK

3 P

A 9

IO _L9

6 P_

1 /G

C LK

2 S

B 9

IO _L9

5 N_

1 /G

C LK

1 P

C 9

IO _L9

5 P_

1 /G

C LK

0 S

D 9

IO _L9

4 N_

A 10

I O_

L 94

P _1

/ VR

E F_

B 10

IO _L9

3 N_

C 10

I O_

L 93

P _1

D 10

IO _L9

2 N_

E 10

I O_

L 92

P _1

E 11

IO _L0

5 N_

A 11

I O_

L 05

P _1

B 11

IO _L0

4 N_

C 11

I O_

L 04

P _1

/ VR

E F_

D 11

IO _L0

3 N_

1 /V

R P_

A 12

IO _L0

3 P_

1 /V

R N_

B 12

IO _L0

2 N_

C 12

I O_

L 02

P _1

D 12

IO _L0

1 N_

B 13

I O_

L 01

P _1

C 13

VRE

N_3

RP_

3/V

RN_

IO _L9

6 N_

5 /G

C LK

7 S

T 8

IO _L9

6 P_

5 /G

C LK

6 P

R 8

IO _L9

5 N_

5 /G

C LK

5 S

P 8

IO _L9

5 P_

5 /G

C LK

4 P

N 8

IO _L9

4 N_

T 7

IO _L9

4 P_

5 /V

R EF

_ 5

R 7

IO _L9

3 N_

P 7

IO _L9

3 P_

N 7

IO _L9

2 N_

M 7

IO _L9

2 P_

M 6

IO _L9

1 N_

T 6

IO _L9

1 P_

5 /V

R EF

_ 5

R 6

IO _L0

5 N_

5 /V

R P_

P 6

IO _L0

5 P_

5 /V

R N_

N 6

IO _L0

4 N_

T 5

IO _L0

4 P_

5 /V

R EF

_ 5

R 5

IO _L0

3 N_

5 /D

4 /A

L T_

V RP

_ 5

P 5

IO _L0

3 P_

5 /D

5 /AL

T _V

R N_

N 5

IO _L0

2 N_

5 /D

R 4

IO _L0

2 P_

5 /D

P 4

IO _L0

1 N_

5 /R

D WR

_ B

T 4

IO _L0

1 P_

5 /C

S _B

T 3

7/V

EF_7

7/V

EF_7

7/V

EF_7

7/V

N_7

VRP

V CC

O _1

F 10

V CC

O _1

F 9

V CC

O _1

E 9

V CC

O _5

M 8

V CC

O _5

L 8

V CC

O _5

L 7

BANK

B A N K 3

BANK

BANK 7

0−

6/V

N_6

VRP

VRE

F_6

VRE

F_6

VRE

F_6

IO _L0

1 N_

C 4

IO _L0

1 P_

B 4

IO _L0

2 N_

D 5

IO _L0

2 P_

C 5

IO _L0

3 N_

0 /V

R P_

B 5

IO _L0

3 P_

0 /V

R N_

A 5

IO _L0

4 N_

0 /V

R EF

_ 0

D 6

IO _L0

4 P_

C 6

IO _L0

5 N_

B 6

IO _L0

5 P_

A 6

IO _L9

2 N_

E 6

IO _L9

2 P_

E 7

IO _L9

3 N_

D 7

IO _L9

3 P_

C 7

IO _L9

4 N_

0 /V

R EF

_ 0

B 7

IO _L9

4 P_

A 7

IO _L9

5 N_

0 /G

C LK

7 P

D 8

IO _L9

5 P_

0 /G

C LK

6 S

C 8

IO _L9

6 N_

0 /G

C LK

5 P

B 8

IO _L9

6 P_

0 /G

C LK

4 S

A 8

V CC

O _0

F 8

V CC

O _0

F 7

V CC

O _0

E 8

I O_

L 01

N _4

/DO

U T

T 14

I O_

L 01

P _4/

INIT

_ B

T 13

I O_

L 02

N _4

/D0

P 13

I O_

L 02

P _4/

D 1

R 13

I O_

L 03

N _4

/D2

/AL

T _V

R P_

N 12

I O_

L 03

P _4/

D 3/A

L T_

V RN

_ 4

P 12

I O_

L 04

N _4

/VR

E F_

R 12

I O_

L 04

P _4

T 12

I O_

L 05

N _4

/VR

P _4

N 11

I O_

L 05

P _4/

V RN

_ 4

P 11

I O_

L 91

N _4

/VR

E F_

R 11

I O_

L 91

P _4

T 11

I O_

L 92

N _4

M 11

I O_

L 92

P _4

M 10

I O_

L 93

N _4

N 10

I O_

L 93

P _4

P 10

I O_

L 94

N _4

/VR

E F_

R 10

I O_

L 94

P _4

T 10

I O_

L 95

N _4

/GC

L K3

N 9

I O_

L 95

P _4/

G CL

K 2P

P 9

I O_

L 96

N _4

/GC

L K1

R 9

I O_

L 96

P _4/

G CL

K 0P

T 9

V CC

O _4

M 9

V CC

O _4

L 10

V CC

O _4

L 9

N_2

RP_

2/V

RN_

EF_

F13

F14

F15

F16

F12

EF_

BANK

B A N K 2

BANK

BANK 6

−6F

256

G_B

AP_

RDW

0−

S he

ild

Con

nel

GND

OUT

7 −11
7 −10

7 −9
7 −8

7 −4

7 −5

7 −6

7 −7

7 −0

7 −1

7 −2

7 −3

6 −8

6 −9

6 −10

6 −11

6 −4
6 −5
6 −6
6 −7

6 −3

6 −2

6 −1

6 −0

5 −9

5 −11

5 −6

5 −10

5 −7

5−

4−

3−

2−

1 −4

1 −5

1 −6

1 −7

1 −8

1 −9

1 −10

1 −11

2 −1
2 −0

2 −3

2 −2

1 −3

1 −2

1 −1

1 −0

0 −11

0 −10

0 −9

0 −8

0 −7

0 −6

0 −5

0 −4

0 −3

0 −2

0 −1

0 −0

F PG

A _R

S T

D CLK

T en

_ SE

0−

1−

2−

3−

4−

5−

6−

7−

G ND

V cco

OE/

ESE

V cco

1 6

V CC

INT

1 7

G ND

1 8

CEO

V cco

2 6

G ND

2 8

V CC

INT

3 5

V cco

3 6

V CC

INT

3 8

D0/

Dat

G ND

4 1

CLK

0.1

−3.

0.1

−3.

0.1

−3.

2−

TDO

RT_t

o_T

DI_

PROM

ROM

AP_

HSW

AP_E

−PB

G_B

SEL

3.3

I_P

ORT_

ROM

O_P

ROM

o_T

DI_

O_P

ROM

TDI

PGA

ass

O_E

O_P

ROM

O_E

−PB

FPG

3.3

Содержание ADSDeSer-50EVM

Страница 1: ...January 2004 User s Guide SBAU091 High Speed Converter Products...

Страница 2: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Страница 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Страница 4: ...here is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is design...

Страница 5: ...he document revision which is current at the time of the writing of this User s Guide To obtain a copy of the following TI documents visit our website at http www ti com or call the Texas In struments...

Страница 6: ...suant to sub part J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equip ment in other environments may cause interf...

Страница 7: ...onfiguration 2 1 2 1 I O Connectors 2 2 2 1 1 Input 2 2 2 1 2 JTAG 2 2 2 1 3 FPGA and PROM Bypass and Configuration 2 3 2 1 4 FPGA Configuration Pins 2 4 2 1 5 Pushbuttons 2 4 2 1 6 Output Connectors...

Страница 8: ...ctors for the ADSDeSer 50EVM 2 5 2 5 Orientation of Ground Connections for the ADSDeSer 50EVM 2 5 3 1 ADSDeSer 50EVM Layer 1 Top 3 2 3 2 ADSDeSer 50EVM Layer 2 Power 3 3 3 3 ADSDeSer 50EVM Layer 3 Mid...

Страница 9: ...r 50EVM is an evaluation fixture designed for the ADS527x family of data converters It is an eight channel LVDS deserializer Topic Page 1 1 Introduction 1 2 1 2 Features 1 2 1 3 Power Supply 1 3 1 4 I...

Страница 10: ...embedded a synchronous clock out put is provided separately along with the eight channels of data The ADSDeSer 50EVM evaluation board will support the analog to digital converter ADC models listed in...

Страница 11: ...he main board power and a 1 8V to 3 3V supply for the output driver supply An onboard regulator supplies 1 5V to power the FPGA 1 4 Indicators There are two LEDs on the board DS1 is used to show the b...

Страница 12: ...2 1 Board Configuration This chapter describes the inputs controls and circuit design of the ADSDeSer 50EVM in detail Topic Page 2 1 I O Connectors 2 2 2 2 Start up Sequence 2 6 Chapter 2...

Страница 13: ...50EVM Overview JTAG BYPASS PINS PROGRAM PUSHBUTTON INP UT CONFIGURATION PINS FPGA RESET PUSHBUTTON 2 1 1 Input The input connector Con1 is used to connect one of the ADS527xEVM LVDS output converter...

Страница 14: ...lowing diagram shows the default and different configu rations for programming Figure 2 2 Default and Alternate Configurations for Programming the ADSDeSer 50EVM J 11 J 12 PROM Bypass FPGA Bypass PROM...

Страница 15: ...is available in the Xi linx Virtex II Handbook Figure 2 3 Default Configurations for FPGA Pins on the ADSDeSer 50EVM JP1 HSWAP_EN M2 M1 M0 2 1 5 Pushbuttons The ADSDeSer 50EVM has two pushbuttons S1 P...

Страница 16: ...ADS527x through a serial interface Refer to the respective ADS527x datasheet and the ADS527xEVM for more details If the standard configuration for the data converter is used then the following diagra...

Страница 17: ...ply power to the ADSDeSer 50EVM board and look for the Power On DS1 LED and DS2 LED to illuminate If DS2 does not illuminate press the Program S1 pushbutton If no LEDs illuminate contact TI customer s...

Страница 18: ...ic diagram and bill of materials for the ADSDeSer 50EVM Note Board layouts are not to scale These are intended to show how the board is laid out they are not intended to be used for manufacturing ADSS...

Страница 19: ...Board Layout 3 2 3 1 Board Layout Figure 3 1 ADSDeSer 50EVM Layer 1 Top...

Страница 20: ...Board Layout 3 3 Schematic and Layout Figure 3 2 ADSDeSer 50EVM Layer 2 Power...

Страница 21: ...Board Layout 3 4 Figure 3 3 ADSDeSer 50EVM Layer 3 Mid Signal...

Страница 22: ...Board Layout 3 5 Schematic and Layout Figure 3 4 ADSDeSer 50EVM Layer 4 Ground...

Страница 23: ...Board Layout 3 6 Figure 3 5 ADSDeSer 50EVM Layer 5 Bottom...

Страница 24: ...V C C O _2 H 11 V C C O _2 G 11 BANK0 B A N K 2 BANK4 BANK 6 XC2V250 6FG256C U2B G N D T1 6 G N D T1 G N D R 15 G N D R 2 G N D P1 4 G N D P3 G N D L11 G N D L6 G N D K1 0 G N D K9 G N D K8 G N D K7 G...

Страница 25: ...sistor R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 3 47 F AVX TAJA476K004R 3216 size Tantalum Capacitor C1 C2 C4 3 330 0603 Chip Resistor R1 R2 R3 R4 1 CLK 0 1 Terminal strip Square J13 1 DTC114EET1 On Se...

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