Texas Instruments ADS7853EVM-PDK, Руководство пользователя, Страница: 5 / 41

ADSxx53
AINM-A (Pin 2)
AINP-A (Pin 1)
AINM-B (Pin 7)
AINP-B (Pin 8)
OPA836
Inverting Configuration
SMA J1
Header JP1.2
AIN_A
AVDD
V
CM
Optional voltage divider and
OPA836 Buffer
VREF
+
-
OPA836
Inverting Configuration
SMA J2
Header JP2.2
AIN_B
AVDD
V
CM
Optional voltage divider and
OPA836 Buffer
VREF
+
-
JP7
JP8
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EVM Analog Interface
Figure 1. ADSxx53EVM Analog Interface Input Connections
Table 1 summarizes the JP1 and JP2 analog interface connections.
Table 1. JP1 - JP2: Analog Interface Connections
Pin Number Signal Description
CHA inverted input. The signal is routed through an OPA836
JP1.2 AIN_A
in the inverting configuration.
CHB inverted input. The signal is routed through an OPA836
JP2.2 AIN_B
in the inverting configuration.
Table 2 lists the SMA analog inputs.
Table 2. SMA Analog Interface Connections
Pin Number Signal Description
Channel A inverted input. The signal is routed through an
J1 AIN_A
OPA836 in the inverting configuration
Channel B inverted input. The signal is routed through an
J2 AIN_B
OPA836 in the inverting configuration.
5 SBAU210A – June 2014 – Revised August 2014 ADS8353EVM-PDK and ADS7853EVM-PDK
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