Connect the EVM and TSW14J57EVM
11
SLAU640 – April 2019
Copyright © 2019, Texas Instruments Incorporated
Setup Procedure
3.3
Connect the EVM and TSW14J57EVM
With the power off, connect the ADC12DJ5200RFEVM to the TSW14J57EVM through the FMC connector
as shown in
. Ensure that the standoffs provide the proper height for robust connector
connections.
3.4
Connect the Power Supplies to the Boards (Power Off)
1. Confirm that the power switch on the TSW14J57EVM is in the off position. Connect the power cable to
a 12-V DC (minimum 3 A) power supply. Ensure the proper supply polarity by confirming that the outer
surface of the barrel connector is GND and the inner portion of the connector is 12 V. Connect the
power cable to the EVM power connector.
2. Confirm that the power switch for the ADC12DJ5200EVM's power supply is in the off position. Connect
the power cable to a 12-V DC (minimum 2 A) power supply. Ensure the proper supply polarity by
confirming that the outer surface of the barrel connector is GND and the inner portion of the connector
is 12 V. Connect the power cable to the EVM power connector.
CAUTION
Ensure the power connections to the EVMs are the correct polarity.
Failure to do so may result in immediate damage.
Leave the power switches in the off position until directed later.
3.5
Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)
Connect a signal generator to the VIN input of the ADC12DJ5200RFEVM through a bandpass filter and
attenuator at the SMA connector. This must be a low-noise signal generator. TI recommends a Trilithic-
tunable bandpass filter to filter the signal from the generator. Configure the signal generator for 2897 MHz,
6 dBm.
When External Clocking is Used
a. Connect a signal generator to the DEVCLK input of the EVM through a bandpass filter. This signal
generator must be a low-noise signal generator. TI recommends a Trilithic-tunable bandpass filter to
filter the signal coming from the generator. Configure the signal generator for the desired clock
frequency in the range of 0.8 to 5.2 GHz. For best performance when using an RF signal generator,
the power input to the CLK SMA connector must be 9 dBm (2.2 Vpp into 50
Ω
). The signal generator
must increase above 9 dB by an amount equal to any additional attenuation in the clock signal path,
such as the insertion loss of the bandpass filter. For example, if the filter insertion loss is 2 dB, the
signal generator must be set to 9 dBm + 2 dB = 11 dBm.
b. Connect a signal generator to the reference signal input of the EVM at REF CLK(J17). Configure the
signal generator for the desired (260MHz) clock frequency. Set the output power to approximately 6–9
dBm.
NOTE:
1.
The Reference clock frequency can be obtained from the ADC12DJ5200RFEVM GUI.
Once the ADC12DJ5200EVM GUI is configured to the desired JMODE mode and clock
rate. The Reference Clock frequency required by the EVM is displayed on first page of
the GUI shown with red square in
2.
Ensure that the DEVCLK and Reference clock sources are frequency-locked using a
common 10-MHz reference to ensure functionality. Frequency locking the input signal
generator to the other generators can also be done if coherent sampling is desired.
3.
Do not turn on the RF output of any signal generator at this time.
4.
When using the ADC in single-input mode, the device uses both edges of DEVCLK for
sampling.
