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ADC12DJxx00
LMX2582
LMK04828
xo
Opt
Sig Gen 2
Opt
Sig Gen 1
Signal
Generator
Balun
Balun
OSC out
Balun
LMX_CLKB
10MHz
Reference
LMK_CLK
CpOut1
10MHz
Reference
CLKIN0
FPGA_JESD_CLK_A
EVM
DEVCLK
10-MHz Reference
To Enable Coherent Sampling
SYSREF
FPGA_JESD_SYSREF
FPGA_JESD_CLK_B
10-MHz
Reference
10-MHz
Reference
DNI
20
SLAU701 – May 2017
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HSDC Pro Settings for Optional ADC Device Configuration
Appendix B
SLAU701 – May 2017
HSDC Pro Settings for Optional ADC Device Configuration
This appendix provides settings for optional ADC device configuration in HSDC Pro.
B.1
Changing the Number of Frames per Multi-Frame (K)
Changing the number of frames per multi-frame output by the JESD204 transmitter (ADC device) is
configured using the K parameter on the
JESD204B
tab in the
Configuration
GUI. This parameter must be
matched by the receiving device, and the SYSREF frequency must also be programmed to a compatible
frequency. Ensure that the K value complies with the
K Min
and
Step
values for the selected JMODE.
Refer to the ADC12DJxx00EVM operating modes table in the ADC12DJxx00EVM data sheet, (
SLVSD97
).
B.2
Customizing the EVM for Optional Clocking Support
Figure B-1
illustrates the ADC12DJxx00EVM clocking system block diagram.
Figure B-1. ADC12DJxx00EVM Clocking System Block Diagram