TVME8240 User Manual Issue 1.2.9
Page 27 of 70
4.2 MPC8240 EPIC Register
The TVME8240 uses the MPC8240 EPIC in serial mode as the board interrupt controller.
4.2.1 EPIC Register Access
The EPIC Registers are part of the MPC8240 Embedded Utility Memory Block (EUMB).
The EUMB base address is set in the EUMBBAR Register.
For the TVME8240 memory map the EUMB base address is set to 0xFCF0_0000.
4.2.2 EPIC Register Settings
4.2.2.1 Global Configuration Register (GCR)
Offset from EUMBBAR: 0x4_1020
The mode bit in the GCR must be set for EPIC mixed mode operation.
4.2.2.2 EPIC Interrupt Configuration Register (EICR)
Offset from EUMBBAR: 0x4_1030
The EICR clock ratio field should be set to 0x2 for optimized interrupt performance.
The EICR SIE bit must be set to enable Serial Interrupt Mode.
4.2.2.3 Serial Interrupt Vector / Priority Registers (SVPR)
The polarity and sense bits in the SVPRs must be configured accordingly to the EPIC Serial Interrupt
Assignment table.
Please refer to chapter “Interrupt Controller” for the EPIC serial interrupt assignment.
4.2.2.4 EPIC Register Programming
The EPIC Programming Guidelines from the MPC8240 manual should be followed.
