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TIP845 User Manual Issue 1.4

Page 9 of 32

4 ID PROM Contents

Address

Function

Contents

0x01

ASCII ‘I’

0x49

0x03

ASCII ‘P’

0x50

0x05

ASCII ‘A’

0x41

0x07

ASCII ‘C’

0x43

0x09

Manufacturer ID

0xB3

0x0B

Model Number

0x39

0x0D

Revision

0x10

0x0F

Reserved

0x00

0x11

Driver-ID Low - Byte

0x00

0x13

Driver-ID High - Byte

0x00

0x15

Number of bytes used

0x14

0x17

CRC

variable

0x19

Offset Error Gain 1

Board dependent

0x1B

Offset Error Gain 2

Board dependent

0x1D

Offset Error Gain 4

Board dependent

0x1F

Offset Error Gain 8

Board dependent

0x21

Gain Error Gain 1

Board dependent

0x23

Gain Error Gain 2

Board dependent

0x25

Gain Error Gain 4

Board dependent

0x27

Gain Error Gain 8

Board dependent

0x29…0x3F

Not used

Figure 4-1 : ID PROM Contents

The ID PROM data is available 200 µs after reset.

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Содержание TIP845

Страница 1: ...2005 D75845800 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com www tews com TEWS TECHNOLOGIES LLC 1 E Liberty Street Sixt...

Страница 2: ...ising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix 0x i e 0x029E that means hexadecimal value 029E For signals on har...

Страница 3: ...ddress 0x0D 16 5 2 3 Sequencer Timer Register SEQTIMER Address 0x0E 17 5 2 4 Sequencer Instruction RAM Address 0x21 0x4F 17 5 3 Additional Registers 20 5 3 1 Interrupt Status Register INTSTAT Address...

Страница 4: ...CTION RAM ADDRESSING 17 FIGURE 5 9 SEQUENCER INSTRUCTION BYTE BREAKDOWN 17 FIGURE 5 10 SEQUENCER INSTRUCTION RAM 19 FIGURE 5 11 INTERRUPT STATUS REGISTER 20 FIGURE 5 12 INTERRUPT VECTOR REGISTER 20 FI...

Страница 5: ...ruction RAM After the last instruction of a programmed sequence has completed the ADC data of all enabled channels are stored in the data RAM The repeat frequency of the sequencer can be programmed by...

Страница 6: ...ier Programmable for gain 1 2 4 and 8 Input Voltage Range 10V for gain 1 5V for gain 2 2 5V for gain 4 1 25V for gain 8 Input Overvoltage Protection 70Vpp Calibration Data Calibration data for gain an...

Страница 7: ...ing time has elapsed The absolute accuracy of the module can be increased by performing a data correction in software using the factory calibration factors stored in the on board ID PROM 3 1 Data Corr...

Страница 8: ...corr corr Offset Gain 32768 1 Value is the corrected result Reading is the data read from the ADC Data Register Gaincorr and Offsetcorr are the correction factors from the ID PROM stored for each gain...

Страница 9: ...er ID High Byte 0x00 0x15 Number of bytes used 0x14 0x17 CRC variable 0x19 Offset Error Gain 1 Board dependent 0x1B Offset Error Gain 2 Board dependent 0x1D Offset Error Gain 4 Board dependent 0x1F Of...

Страница 10: ...R W 0x02 DATAREG ADC Data Register 16 R 0x05 STATREG ADC Status Register 8 R 0x07 CONVERT ADC Conversion Start Register 8 W 0x09 INTSTAT Input Interrupt Status Register 8 R W 0x0B SEQCONT Sequencer Co...

Страница 11: ...ration after settling time has elapsed R W 0 9 ASTC Automatic Settling Time Control 0 OFF Normal Mode A conversion must be initiated manually in the CONVERT register 1 ON Automatic Mode A conversion i...

Страница 12: ...FF 1 000000 CH1 CH1 010111 CH24 CH24 011000 CH25 N A 101111 CH48 N A 110000 N A N A 111111 N A N A N A ADC Input connected to GND R W 0x3F Figure 5 2 ADC Control Register A write to this register sets...

Страница 13: ...her bits of the register by hardware This allows direct processing of the data as a 16 bit two s complement integer value Bit Symbol Description Access Reset Value 15 2 Stores the converted 14 bit dat...

Страница 14: ...Mode is ON this bit is set automatically after the settling time has elapsed This bit must be read as 0 before the conversion data is read from the DATAREG register R 0 Figure 5 5 ADC Status Register...

Страница 15: ...be generated if any bit is set in the SEQSTAT register sequencer data valid or sequencer error R W 0 0 SEQ ON Sequencer Start Stop Control 0 Stops the sequencer after the last instruction 1 Starts th...

Страница 16: ...ag always read as 0 R W 0 1 DATA OF ERROR Data Overflow Error Flag Set by the sequencer if the last sequencer instruction is done and the Data Available Flag of the previous sequence has not yet been...

Страница 17: ...Address 0x21 0x4F The Sequencer Instruction RAM is a 24 x 8 bit wide RAM which is accessible in the I O space In each sequencer instruction byte configures either one differential ADC channel or two s...

Страница 18: ...equencer will pass over the ADC Channel 1 Sequencer converts the ADC Channel and updates the ADC Data in the Sequencer Data RAM at the end of the sequence If SE DIFF 1 this bit is ignored R W 0 3 2 GA...

Страница 19: ...24 differential channels 1 to 24 available Mixed mode is possible E g channel 1 to channel 8 selected as differential inputs equivalent to single ended inputs 1 16 and channel 17 to channel 48 as sing...

Страница 20: ...s controlled by the settling time controller If interrupts are enabled CONTREG register bit 10 is set to 1 and Automatic Settling Time Mode is OFF CONTREG register bit 8 is set to 0 this interrupt is...

Страница 21: ...ntial Channel 12 Single Ended Channel 23 16 R 0x2E SDRAM24 Single Ended Channel 24 16 R 0x30 SDRAM25 Differential Channel 13 Single Ended Channel 25 16 R 0x32 SDRAM26 Single Ended Channel 26 16 R 0x58...

Страница 22: ...r has to wait until the ADC_SETTL flag reads 0 Then the conversion can be started by writing to the CONVERT register If the Automatic Settling Time Control is activated the conversion starts automatic...

Страница 23: ...encer Data RAM Afterwards the DATA_AV flag must be cleared by writing a 1 to the Sequencer Status Register SEQSTAT bit 0 Only the enabled channels are updated not enabled channels in the Sequencer Ins...

Страница 24: ...r Error Error occurs if the programmed sequencer time is shorter than the sequence itself Sequencer Timer Mode only Sequencer stops after the last instruction is done Timer Error Flag is set If it is...

Страница 25: ...the IRQ after conversion IRQC 1 The channel is now converted without any further user action After completion of the conversion an interrupt is issued which signals that the conversion data is availa...

Страница 26: ...errupt in the Interrupt Status Register INTSTAT SETTL_READY 1 After completion of the conversion an interrupt is issued which signals that the conversion data is available in the DATAREG register Writ...

Страница 27: ...TIP845 User Manual Issue 1 4 Page 27 of 32 Figure 6 3 Flow of fastest conversion of a specific single channel Conversion time is approx 2 5 s as long as neither the channel nor the gain is changed...

Страница 28: ...Sequencer Interrupt SEQ_INT_ENA and start the sequencer in the Sequencer Control Register SEQCONT After completion of the sequence an interrupt is issued which signals that the conversion data is avai...

Страница 29: ...converted and program the gain and mode of these channels in the Sequencer Instruction RAM Set the Sequencer Timer Register SEQTIMER to 0x0000 Start the sequencer in the Sequencer Control Register SE...

Страница 30: ...4 15 ADC Input 8 ADC Input 15 16 ADC Input 8 ADC Input 16 17 ADC Input 9 ADC Input 17 18 ADC Input 9 ADC Input 18 19 ADC Input 10 ADC Input 19 20 ADC Input 10 ADC Input 20 21 ADC Input 11 ADC Input 21...

Страница 31: ...put 20 ADC Input 39 42 ADC Input 20 ADC Input 40 43 ADC Input 21 ADC Input 41 44 ADC Input 21 ADC Input 42 45 ADC Input 22 ADC Input 43 46 ADC Input 22 ADC Input 44 47 ADC Input 23 ADC Input 45 48 ADC...

Страница 32: ...CONVERT Register to perform the dummy conversions If the sequencer is to be used these two dummy conversions are absolutely necessary If one of our software drivers is used these two dummy conversions...

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