Tews Technologies TIP845, Руководство пользователя

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TIP845 User Manual Issue 1.4 Page 20 of 32
5.3 Additional Registers
5.3.1 Interrupt Status Register INTSTAT (Address 0x09)
Bit Symbol Description Access Reset
Value
7:3 -
Reserved
Write: don't care
Read: always reads as '0'
R 0
2 SEQ
READY Sequencer Interrupt Pending Flag (bit is controlled by the
sequencer logic)
If sequencer interrupts are enabled (SEQCONT register
bit 1 set to '1’) and a sequencer interrupt is pending (any
of the SEQSTAT register bits [3:0] is ‘1’) the sequencer
interrupt pending flag is read as ‘1’.
The interrupt is cleared by writing ’1’ to the
corresponding status bits in the SEQSTAT register. R/W 0
1 SETTL
READY SETTL_READY Interrupt Flag (bit is controlled by the
settling time controller)
If interrupts are enabled (CONTREG register bit 10 is set
to ‘1’) and
Automatic Settling Time Mode is OFF
(CONTREG register bit 8 is set to ‘0’) this interrupt is
generated, if the settling time is expired.
The interrupt is cleared by writing ’1’ to this bit.
R/W 0
0 ADC
READY ADC_READY Interrupt Flag (bit is controlled by the ADC
controller)
If interrupts are enabled (CONTREG register bit 11 is set
to ‘1’) this interrupt is generated, if a data conversion is
done.
The interrupt is cleared by writing ’1’ to this bit. R/W 0
Figure 5-11: Interrupt Status Register
5.3.2 Interrupt Vector Register IVEC (Address 0x11)
Bit Symbol Description Access Reset
Value
7:0 IVEC Interrupt Vector R/W 0
Figure 5-12: Interrupt Vector Register
5.4 Memory Addressing
In Sequencer Mode the converted ADC data is accessible in the IP Memory Space.