TCP460 User Manual Issue 1.1
Page 12 of 32
4.2.1 UART Register Sets
The Device Configuration Space provides a register set for each of the 8 internal UARTs.
UART Register Set
Register Set Offset
Serial Channel 0
0x0000
Serial Channel 1
0x0200
Serial Channel 2
0x0400
Serial Channel 3
0x0600
Serial Channel 4
0x0800
Serial Channel 5
0x0A00
Serial Channel 6
0x0C00
Serial Channel 7
0x0E00
Figure 4-3 : UART Register Set Offset
Each UART Register Set contains the 16C550 Compatible 5G Register Set. It also provides a way to
directly access the FIFO from the PCI bus.
Offset Address Description
Access Data Width
0x000 – 0x00F
UART Channel Configuration Registers
First 8 registers are 16550 compatible
R/W
8, 16, 32
0x010 – 0x07F
Reserved
-
-
0x080 – 0x093
Channel 0: Device Configuration Registers
All other channels: Reserved
R/W
8, 16, 32
0x094 – 0x0FF
Reserved
-
-
Read FIFO – 64 bytes of RX FIFO data
R
8, 16, 32
0x100
Write FIFO – 64 bytes of TX FIFO data
W
8, 16, 32
0x140 – 0x17F
Reserved
-
-
0x180 – 0x1FF
Read FIFO with errors –
64 bytes of RX FIFO data + LSR
R 16,
32
Figure 4-4 : UART Register Set
Embedded in the UART 0 Register set are the Device Configuration Registers.
