TCP460 User Manual Issue 1.1
Page 11 of 32
4.2 Device Configuration Space
PCI Base Address:
XR17D158 PCI Base Address 0 (Offset 0x10 in PCI Configuration
Space).
The Device Configuration Space is accessible directly from the PCI bus and is mapped into 4K of the
PCI bus memory address space. It contains the Device Configuration Registers and the UART
Configuration Registers.
Device Configuration Space
Content
PCI Address
Size
(Bit)
UART 0 Configuration Registers PCI Base Address 0 + (0x0000 to 0x007F)
32
Device Configuration Registers
PCI Base Address 0 + (0x0080 to 0x009F)
32
UART 0 Configuration Registers PCI Base Address 0 + (0x0100 to 0x01FF)
32
UART 1 Configuration Registers PCI Base Address 0 + (0x0200 to 0x03FF)
32
UART 2 Configuration Registers PCI Base Address 0 + (0x0400 to 0x05FF)
32
UART 3 Configuration Registers PCI Base Address 0 + (0x0600 to 0x07FF)
32
UART 4 Configuration Registers PCI Base Address 0 + (0x0800 to 0x09FF)
32
UART 5 Configuration Registers PCI Base Address 0 + (0x0A00 to 0x0BFF)
32
UART 6 Configuration Registers PCI Base Address 0 + (0x0C00 to 0x0DFF)
32
UART 7 Configuration Registers PCI Base Address 0 + (0x0E00 to 0x0FFF)
32
Figure 4-2 : Device Configuration Space
All registers can be accessed in 8, 16 or 32 bit width with exception to one special case: When reading
the receive data together with its LSR register content, the host must read them in 16 or 32 bits format
in order to maintain integrity of the data byte with its associated error flags.
