73S8023C Demo Board User Manual
UM_8023C_027
8
Rev. 1.3
Item
#
Schematic/
Silkscreen
Reference
Name
Function
Test Points:
10
TP1
Pin 18*
(VDDF_ADJ)
VDD voltage fault adjustment. The pin to the left is
connected to the VDDF_ADJ pin of the 73S8023C and
the pin to the right is GND. When either a resistor R3,
or a resistor network R1 and R3 is populated on the
board, it adjusts the VDD fault level that internally
triggers a card deactivation sequence.
By default, the resistors R1 and R3 are not connected.
This provides a VDD fault level of 2.3V typical (internally
set to the 73S8023C). Refer to the
73S8023C Data
Sheet
for further information about VDD fault level and
determination of the resistor values.
*The silkscreen is in error. It is shown as ‘Pin 18’ when
actually it is Pin 17.
20
TP2
Factory Test
Factory test pin. Do not connect.
7
12
6
14
5
4
TP3
TP4
TP5
TP6
TP7
TP8
VCC
I/O
RST
C8
CLK
C4
2-pin test points for each respective smart card signal.
The pin label name is the respective signal (i.e. VCC,
CLK) and the 2nd pin is GND.
Figure 3: 73S8023C Demo Board Connectors, Jumpers and Test Points
