Teridian 73S8023C, Руководство пользователя

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UM_8023C_027 73S8023C Demo Board User Manual
Rev. 1.3 7
3 Hardware Description
3.1 Demo Board Connectors, Jumpers and Test Points
Table 1 describes the 73S8023C Demo Board connectors, jumpers and test points. The Item # in Table 1
refers to
Figure 3.
Table 1: 73S8023C Demo Board Connector, Jumper and Test Points
Item
#
Schematic/
Silkscreen
Reference
Name
Function
Connectors:
1 J2 Auxiliary Interface /
5V Board Power
73S8023C auxiliary interface (I/OUC, AUX1UC,
AUX2UC), external clock (SCLK) and interrupt (
OFF
)
pins. The external clock (SCLK) can be left open when
JP1 is in position XTAL.
The 5V power supply is unused and must be left open
and JP2 must be inserted in position 3.3V.
9 J4 3.3V Board Power /
Digital Control
Signals
3.3V board power supply and the 73S8023C host
control signals RSTIN,
CMDVCC
, 5V/
#V
, PWRDWN,
CLKDIV2 and CLKDIV1.
18 J5 Smart Card
Connector
Smart card connector.
When inserting a card (credit card size format), contacts
must face up.
11 J6 Smart Card
Connector
SIM/SAM smart card format connector.
J6 is wired in parallel to the smart card connector J5
(underneath the PCB). No SIM/SAM should be inserted
when using the credit-card size connector J5.
Jumpers:
3 JP1 Clock Selection Jumper to select between a crystal or an external clock
as the frequency reference to the device. The default
setting is for a crystal.
19 JP2 VPC Select Jumper to select the value of the power supply for the
smart card DC-DC converter (73S8023C input VPC).
To support both card voltages, JP2 must be set to
position 3.3V. The default setting is 3.3V.
2 JP3 VDD Select Jumper to select the digital voltage which supplies the
73S8023C.
Must be set for 3.3V.
8 JP4 – Not used.
16
15 JP5
JP6 Card Polarity
Detect Select
The setting of JP5 and JP6 depends on the type of
smart card connector used (nominally open or closed)
and which 73S8023C card presence switch input is
used. The switch is nominally open for the 73S8023C
Demo Board. The jumpers can be set to:
1. Use of PRES (default): JP5 set to PRES; JP6 set
to VDD.
2. Use of
PRES:
JP5 set to PREB; JP6 set to GND.
13 JP7 CLKSEL Three pin header. Set to VDD for sync operation.
17 JP8 CS Three pin header. Set to VDD for normal operation.
21 JP9 CLKOUT Two pin header. Outputs the buffered version of XTALIN.
22 JP10 STROBE Two pin header. Controls clock signal when CLKSEL=1.