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73S8009C Demo Board User Manual 

UM_8009C_059

 

 

14 

 

Rev. 1.3 

1

2

S1

SW

1
2

JP7

CS

Disable

Note: VPCIN

must be

between 2.7

and 6.5V

3.3V

1
2
3
4
5
6
7
8
9

10

J4

TSM_110_01_L_SV

C12

30pF

C3

0.1uF

IOUC

1

AUX1UC

2

AUX2UC

3

CMDVCC5

4

CMDVCC3

5

RSTIN

6

CLKIN

7

RDY

8

O

FF_

A

CK

9

T

EST

1

1

0

O

FF_

RE

Q

1

1

CS

1

2

PR

ES

1

3

PR

ES

1

4

VP

1

5

GND

17

RST

18

VCC

19

AUX2

20

AUX1

21

IO

22

VBUS

23

ON/OFF

24

VBAT

2

5

VPC

2

6

L

IN

2

7

GN

D

2

8

VD

D

2

9

T

EST

2

3

0

GN

D

3

1

OF

F

3

2

C

LK

1

6

S

LU

G

3

3

U1

73S8009C

VPCIN

+

C1

10uF

3.3V

VPC

SELECT

L1

3.3V

1
2
3
4
5
6
7
8
9

10

J3

SSM_110_L_SV

AUX1UC
AUX2UC

IOUC

RDY

OFF_ACK

R13
Rd

R10
Ru

1

TP9

AUX1
AUX2

IO

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CMDVCC#

CLKIN

C9

30pF

OF

F

C11

0.47uF

C1

1

C2

2

C3

3

C5

4

C6

5

C7

6

SW

1

7

SW

2

8

J6

SIM/SAM Connector

RST

CLK

CMDVCC%

CMDVCC%

CMDVCC%

CMDVCC%

CMDVCC%

1

TP1

C2

0.1uF

RSTIN

1
2

TP3

VC

C

1

R

ST

2

C

L

K

3

C4

4

GN

D

5

VPP

6

I/

O

7

C8

8

SW

-1

9

SW

-2

1

0

J5

Smart Card Connector

VCC

R8
Ru

R9
Ru

R11
Rd

VPCIN

R12
Rd

R7 0

USR7

CMDVCC#

1
2
3
4
5
6
7
8
9

10

J1

SSM_110_L_SV

CMDVCC3

OFF_REQ
CS

C4

4.7uF

1
2
3

JP6

1
2
3

JP5

1
2

TP5

1

2

3

JP3

1
2

TP7

1
2

TP8

1
2

TP4

1
2

TP6

1
2

JP4

3.3V

Note: JP4 pins 1

and 2 must not be

connected with JP2

pins 1 and 2 at the

same time.

GND

C8

DNI

SC4

TP3 to TP8, C9, C11 and

C12 are to be placed

very close to the pads

of J5

PRES

PRES

CARD DETECT

POLARITY

SELECT

CLK

RDY

VDD

VDD

1

2

3

JP2

OFF_ACK

GND

R8 to R13 and C36 to be

placed within 1cm of

J7.

DNI

PRES

J1 must be aligned with J2 and J3 must be

aligned with J4 in order for this daughter

board to be stacked on another.

OFF_REQ

+3.3V

DNI

CS

DNI

RSTIN

VPCIN

PRES

J1 and J3 are placed on the bottom.  J2 and J4

are placed on the top side.

RST

VPCIN

GND

1

TP2

J1 and J3 must be aligned with J8 and J9 on the

1121 evaluation board (E1121T8) respectivly in

order for this board to be stacked on it.

CMDVCC5

DNI

VCC

SCLK

C4

C1, C2, C3 and L1 must be placed

within 5mm of the U1 pins and

connected by thick track (wider

than 0.5mm)

VDD

SC8

DNI

GND

SIO

Note: JP4 pins 1

and 2 should only

be connected when

3.3V is not sourced

from the mating

board (if

applicable)

OFF

GND

1
2
3
4
5
6
7
8
9

10

J2

TSM_110_01_L_SV

I/O

5  73S8009C Demo Board Schematics, PCB Layouts and Bill of Materials 

5.1 

Schematics 

 

 

 

 
 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 
 
 
 
 
 
 
 
 

 

 

 

 

Figure 4: 73S8009C Electrical Schematic 

 
 
 

Содержание 73S8009C

Страница 1: ...Simplifying System IntegrationTM 73S8009C Demo Board User Manual February 10 2010 Rev 1 3 UM_8009C_059...

Страница 2: ...the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves...

Страница 3: ...t Points 9 4 Design Considerations 12 4 1 General Layout Rules 12 4 2 Optimization for Compliance with EMV 12 4 3 Power Supply Input Configurations 12 4 3 1 USB Power 12 4 3 2 Single Supply Power 12 4...

Страница 4: ...ew 15 Figure 7 73S8009C Demo Board Top Signal Layer 16 Figure 8 73S8009C Demo Board Middle Layer 1 Ground Plane 16 Figure 9 73S8009C Demo Board Middle Layer 2 Supply Plane 17 Figure 10 73S8009C Demo B...

Страница 5: ...e used in conjunction with the 73S12xxF evaluation platform 1 1 Package Contents Figure 1 73S8009C Demo Board The 73S8009C Demo Board Kit includes A 73S8009C Demo Board Rev 1 The following documents 7...

Страница 6: ...oltage card interface 0 3 to VCC 0 3 VDC Pin Voltage LIN pin 0 3 to 6 5 VDC ESD Tolerance Card interface pins 6 kV ESD Tolerance Other pins 2 kV Pin Current 200 mA Operation outside these rating limit...

Страница 7: ...ound pin Pin 9 Table 3 J4 Pin Descriptions Pin Pin Name Function 1 CMDVCC Controls the turn on output voltage value and turn off of VCC 2 CMDVCC 3 RSTIN Controls the card reset signal 4 RDY Indicates...

Страница 8: ...8 to from the card 5 OFF Interrupt signal to the processor Indicator of card presence and any card fault conditions 6 GND Ground 7 GND Ground 8 GND Ground 9 VPC IN Must be between 2 7 V and 6 5 V 10 V...

Страница 9: ...UM_8009C_059 73S8009C Demo Board User Manual Rev 1 3 9 3 Jumpers Switches and Test Points The items marked in Figure 3 are described in Table 5 Figure 3 73S8009C Demo Board Description...

Страница 10: ...t VBUS Test point C4 CLK RST VCC I O C8 VBAT Input VBUS Input Two pin test points for each respective smart card signal The pin label name is the respective signal i e VCC CLK and the other pin is GND...

Страница 11: ...ee board errata in the appendix for JP6 16 J5 Smart Card Connector Smart card connector When inserting a card credit card size format contacts must face up 17 JP7 CS Disable CS Disable Jumper Insertio...

Страница 12: ...the smart connector to ground These capacitors serve as filters for CLK and RST signals in the case of long traces or test equipment perturbations The capacitor on CLK reduces ringing on the trace re...

Страница 13: ...hed it can set the OFF_ACK signal high to shut off the 73S8009C If there is no need for the host to perform any shutdown tasks the OFF_ACK pin can be left open and it follows the state of the OFF_REQ...

Страница 14: ...C3 OFF_REQ CS C4 4 7uF 1 2 3 JP6 1 2 3 JP5 1 2 TP5 1 2 3 JP3 1 2 TP7 1 2 TP8 1 2 TP4 1 2 TP6 1 2 JP4 3 3V Note JP4 pins 1 and 2 must not be connected with JP2 pins 1 and 2 at the same time GND C8 DNI...

Страница 15: ...UM_8009C_059 73S8009C Demo Board User Manual Rev 1 3 15 5 2 73S8009C PCB Layouts Figure 5 73S8009C Demo Board Top View Figure 6 73S8009C Demo Board Bottom View...

Страница 16: ...73S8009C Demo Board User Manual UM_8009C_059 16 Rev 1 3 Figure 7 73S8009C Demo Board Top Signal Layer Figure 8 73S8009C Demo Board Middle Layer 1 Ground Plane...

Страница 17: ...UM_8009C_059 73S8009C Demo Board User Manual Rev 1 3 17 Figure 9 73S8009C Demo Board Middle Layer 2 Supply Plane Figure 10 73S8009C Demo Board Bottom Signal Layer...

Страница 18: ...10_L_SV SSM_110_L_SV X SSM_110_L_SV Samtec 2 J2 J4 TSM_110_01_L_SV TSM_110_01_L_SV X TSM_110_01_L_SV Samtec 1 J5 Smart Card Connector ITT_CCM02 2504 401 1715 ND CCM02 2504LFT ITTCannon 1 J6 SIM SAM Co...

Страница 19: ...ation The following 73S8009C documents are available from Teridian Semiconductor Corporation 73S8009C Data Sheet 73S8009C Demo Board User Manual 9 Contact Information For more information about Teridi...

Страница 20: ...ected pin number for OFF_ACK in pin description 1 3 2 10 2010 Formatted in the new Teridian style Added Section 1 1 Package Contents Added Section 1 2 Safety and ESD Notes Added Table 3 J4 Pin Descrip...

Страница 21: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Maxim Integrated 73S8009C DB...

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