73S8009C Demo Board User Manual
UM_8009C_059
12
Rev. 1.3
4 Design Considerations
4.1
General Layout Rules
Follow these layout rules:
•
Route I/O and auxiliary signals away from card interface signals.
•
Keep CLK trace as short as possible and with minimal bends in the trace. If possible, keep routing of
the CLK trace to one layer (avoid vias to other layers). Keep CLK trace away from other traces
especially RST, I/O and VCC. Filtering of the CLK trace is allowed for noise purposes. Up to 30 pF
to ground is allowed at the CLK pin of the smart card connector. Also, the zero
Ω
series resistor (R7)
can be replaced with a small resistor for additional filtering (no more than 100
Ω
).
•
Keep VCC trace as short as possible. Make trace a minimum of 0.5 mm thick. Also, keep VCC away
from other traces especially RST and CLK.
•
Keep RST trace away from VCC and CLK traces. Up to 30 pF to ground is allowed for filtering.
•
Keep 0.1
µ
F close to VDD pin of the device and directly take other end to ground.
•
Keep 0.1
µ
F and 10
µ
F close to VPC pin of the device and directly take other end to ground.
•
Keep 4.7
µ
F close to VP pin of the device and directly take other end to ground.
•
Keep 0.47
µ
F close to VCC pin of the smart card connector and directly take other end to ground.
4.2
Optimization for Compliance with EMV
Default configuration of the Demo board contains a 27 pF capacitor (C12) from the CLK pin of the smart
connector to ground and a 27 pF capacitor (C13) from the RST pin of the smart connector to ground.
These capacitors serve as filters for CLK and RST signals in the case of long traces or test equipment
perturbations. The capacitor on CLK reduces ringing on the trace, reduces coupling to other traces and
slows down the edge of the CLK signal. The capacitor on RST helps the perturbation specification in a
noisy environment. The filter capacitors can be useful in the EMV test environment and have no effect on
NDS testing
C12 and C13 are represented on both schematic and BOM. These capacitors are optional filter
capacitors on the smart card lines CLK and RST, respectively for each card interface. These capacitors
may be adjusted (value, not to exceed 30 pF) or removed to optimize performance in each specific
application (PCB, card clock frequency, compliance with applicable standards etc).
4.3
Power Supply Input Configurations
4.3.1 USB Power
The USB configuration uses the power supplied by the VBUS (4.4 to 5.5 V) and an optional VBAT input
that automatically switches from the VBUS to VBAT when the VBUS power is removed. This switch over
is done smoothly and does not cause any disruption of the operation of the 73S8009C and the VDD
output supply. The operation of the ON/OFF switch is overridden when VBUS is applied. The 73S8009C
and VDD output will always be active while the VBUS voltage is applied. The ON/OFF switch is enabled
when running off VBAT. When using this configuration, the VPC input should not be connected to any
other power source.
4.3.2 Single Supply Power
The single supply configuration should leave the VBUS and VBAT pins unconnected and only connect
the power supply to VPC (2.7 to 6.0 V).
