71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 7 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
I0
I1
I2
I3
MUX
CK38
CK
VREF
CKTEST
CE
32-bit Compute
Engine
MPU
(80515)
CE
CONTROL
OPT_RX
OPT_TX
RESETZ
V1
EMULATOR
PORT
CE
_
B
US
Y
OPTICAL
I/F
UART
TX
RX
XF
E
R
BU
SY
CE PROG
RAM
(4KB)
COM0..3
LCD DISPLAY
DRIVER
RTC
DATA
00-FF
PROG
000-7FF
DATA
0000-FFFF
PROG
0000-FFFF
MPU XRAM
(2KB)
0000-07FF
DIGITAL I/O
CONFIG
RAM
(I/O RAM)
2000-20FF
I/O R
A
M
CE DATA
RAM
(1KB)
MEMORY
SHARE
3000-3FFF
1000-13FF
RTCLK
MUX_SYNC
CKCE
CKMPU
V2
CE_RUN
CE_LOAD
CE_EN
RTM_EN
COMP_INT
COMP_STAT
WATCHDOG
POWER FAULT
GENERATOR AND
COMPARATORS
LCD_CLK
LCD_MODE
DIO_GP
RTC_SET
4.9MHz
4.9MHz
GNDD
V3P3A
V3P3D
VBAT
VOLT
REG
2.5V to logic
V2P5
MPU_DIV
SUM_CYCLES
PRE_SAMPS
CKOUT_EN
VLCD
TMUXOUT
FAULTZ
WAKE
VBIAS
DMUX
TMUX
CONFIGURATION
PARAMETERS
VDRV
GNDA
I4
TEMP
September 9, 2006
CK_GEN
CK32
CK_EN
CLK
divider
VOLTAGE
BOOST
LCD_BSTEN
LCD_IBST
VREF
VREF_DIS
MUX
CTRL
MUX_DIV
CHOP_EN
STRT
I5
MUX
CKFIR
4.9MHz
MUX_SYNC
RTM
RTM
SEG20..23
DIO_0..3
SEG28/DIO8 ..
SEG31/DIO11
GNDA
GNDD
FAULT_PULSE
STROBE
FAULT_PULSE
STROBE
TEST3
LCD_FS
LCD_MODE
LCD_EN
GNDD
LCD_NUM
DIO_OUT
DIO_IN
LCD_NUM
RTC_HOLD
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DGND
IBIAS
WDTR_EN
V2 OK
V3 OK
OPTRX
ANALOG
DIGITAL
STROBE
MUX_ALT
SEG24/DIO4 ..
SEG27/DIO7
SEG32/DIO12 ..
SEG41/DIO21
SCL
SDA
FLASH
(64KB)
EEWRSLOW
EERDSLOW
V3P3A
FIR_LEN
FIR
FILTER
CK_10M
CK_MPU
reserved
SEG0..2, SEG3/SCLK,
SEG4/SSDATA,
SEG5/SFR, SEG7..19
EEPROM
INTERFACE
DIO_EEX
PLL_2.5V
ECK_DIS
OPT_TXDIS
GNDD
∆Σ
ADC
CONVERTER
+
-
VREF
RTCLK
CE_BUSY
XFER_BUSY
VBIAS
V3P3
V2P5
SEG6/SRDY
VBIAS
VBIAS
PLLOUT
SSI
INEUTRA
L
INEUTRAL
38kHz
19.66MH
z
FAULT_PULSE
Figure 1: IC Functional Block Diagram
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