MLT2 User Manual
10
www.terasic.com
April 12, 2016
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Figure 2-3
shows the block diagram of MTL2. The IDE connector houses all the wires from
peripheral interfaces, connecting to the FPGA of a development kit through the IDE cable and ITG
adapter.
Figure 2-3 Block Diagram of MTL2
Figure 2-4
illustrates the connection for MTL2 to the Terasic FPGA boards.
Figure 2-4 Connection Diagram of MTL2 Kit with Terasic FPGA boards
Содержание MTL2
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