Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 62 www.terasic.com
September 6, 2019

A x86 PC

Windows 10 64bit operation system Installed

One USB Port

Quartus Prime 18.0 or Later Installed

SoC EDS 18.0 or Later Installed

Win32 Disk Imager Installed
4 4 . . 3 3 A A X X I I b b r r i i d d g g e e s s i i n n I I n n t t e e l l S S o o C C F F P P G G A A
In Intel SoC FPGA, the HPS logic and FPGA fabric are connected through the AXI (Advanced
extensible Interface) bridge. For HPS logic to communicate with FPGA fabric, Intel system
integration tool
Platform Designer should be used for the system design to add HPS component.
From the AXI master port of the HPS component, HPS can access those Qsys components whose
memory-mapped slave ports are connected to the master port.
The HPS contains the following HPS-FPGA AXI bridges.
 
FPGA-to-HPS Bridge


HPS-to-FPGA Bridge
 
Lightweight HPS-to-FPGA Bridge
Figure 4-1 shows a block diagram of the AXI bridges in the context of the FPGA fabric and the L3
interconnect to the HPS. Each master (M) and slave (S) interface is shown with its data width(s).
The clock domain for each interconnect is noted in parentheses.
Figure 4-1 AXI Bridge Block Diagram
The HPS-to-FPGA bridge is mastered by the level 3 (L3) main switch and the lightweight