Terasic Altera Dual-XAUI, Руководство пользователя

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differential clock..
E9 PHYRESET LVTTL PHY Reset, Active low.
H5 PLOSB1 LVTTL PMD Loss of Signal Channel 1.
H11 PLOSB2 LVTTL PMD Loss of Signal Channel 2.
A10 PRTAD01 CMOS Channel 1 PHY Address LSB.
A9 PRTAD02 CMOS Channel 2 PHY Address LSB
B9 PRTAD1 CMOS PHY Address bit 1.
C9 PRTAD2 CMOS PHY Address bit 2.
B10 PRTAD3 CMOS PHY Address bit 3.
C10 PRTAD4 CMOS PHY Address bit 4.
T14 RB_CAL Analog Not used.
R14 RB_CAL_VSS Analog Not used.
V1 RCLKN_1 Differential
CML Analog Recovered Clock from CDR Channel
1 negative leg.
V10 RCLKN_2 Differential
CML Analog Recovered Clock from CDR Channel
2 negative leg.
U1 RCLKP_1 Differential
CML Analog Recovered Clock from CDR Channel
1 positive leg.
V9 RCLKP_2 Differential
CML Analog Recovered Clock from CDR Channel
2 positive leg.
T8 RDICM_1 Analog Receiver Common Mode Input channel 1.
V18 RDICM_2 Analog Receiver Common Mode Input channel 2..
K5 SCK1 LVTTL SPI ROM Clock for channel 1.
M11 SCK2 LVTTL SPI ROM Clock for channel 2.
H10 SER_BOOT LVTTL SPI ROM Boot Enable active high.
V7 SFI_RX_N1 Differential
CML Receiver Serial Data channel 1, negative leg.
V16 SFI_RX_N2 Differential
CML Receiver Serial Data channel 2, negative leg.
V6 SFI_RX_P1 Differential
CML Receiver Serial Data channel 1, positive leg.
V15 SFI_RX_P2 Differential
CML Receiver Serial Data channel 2, positive leg.
V3 SFI_TX_N1 Differential
CML Transmitter Serial Data channel 1, negative
leg.
V12 SFI_TX_N2 Differential
CML Transmitter Serial Data channel 2, negative
leg.
V4 SFI_TX_P1 Differential
CML Transmitter Serial Data channel 1, positive
leg.
V13 SFI_TX_P2 Differential
CML Transmitter Serial Data channel 2, positive
leg.