Terasic Altera Dual-XAUI, Руководство пользователя

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E7 LASI1 CMOS Link Alarm Status Interrupt Channel 1.
K10 LASI2 CMOS Link Alarm Status Interrupt Channel 2.
D8 MDC2 CMOS Management Data Clock single device
(default), Management Data Clock channel 2
for dual MDIO device.
E8 MDIO2 CMOS Management Data I/O for single MDIO
device (default), Management Data I/O
channel 2 for dual MDIO device.
G5 MISO1 LVTTL Master Input/Slave Output Channel 1.
G12 MISO2 LVTTL Master Input/Slave Channel 2.
G10 MOD_ABS1 CMOS Module Absent Channel 1.
N8 MOD_ABS2 CMOS Module Absent Channel 2.
F5 MOSI1 LVTTL Master Output to Slave Input channel 1.
F12 MOSI2 LVTTL Master Output to Slave Input channel 2.
G7 NC/MDC_1 CMOS No Connect for single MDIO device (default),
Management Data Clock channel 1 for dual
MDIO device.
G8 NC/MDIO_1 CMOS No Connect for single MDIO device (default),
Management Data I/O channel 1 for dual
MDIO device.
M1 NVMA1SEL LVTTL Non-volatile Memory Select
G9 NVMPROT CMOS Non-volatile Memory Protect
E10 OPINLVL LVTTL Optical Control Input Level.
D10 OPOUTLVL LVTTL Optical Control Output Level.
L4 OPRXLOS1 CMOS Optical Receiver Loss of
Signal Channel 1.
L12 OPRXLOS2 CMOS Optical Receiver Loss of
Signal Channel 2.
H8 OPTXFLT1 CMOS Optical Transmitter Fault
Indicator Channel 1.
J14 OPTXFLT2 CMOS Optical Transmitter Fault
Indicator Channel 2.
K4 OPTXRST1_1 LVTTL Optical Module Reset Channel 1.
K12 OPTXRST1_2 LVTTL Optical Module Reset Channel 2.
H6 PCDRLK1 LVTTL PMD CDR Lock Detect Channel 1.
M12 PCDRLK2 LVTTL PMD CDR Lock Detect Channel 2.
G6 PCMULK1 LVTTL PMD CMU Lock Detect Channel 1.
L11 PCMULK2 LVTTL PMD CMU Lock Detect Channel 2..
R10 PEXTCLK156_N Reference Clock Channel negative leg of a
differential clock.
T10 PEXTCLK156_P Reference Clock Channel positive leg of a