Terasic Altera Dual-XAUI, Руководство пользователя

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Table 3-1 shows the pin description of the HSMC connector.
Table 3-1 The pin mappings of the HSMC connector
HSMC Schematic Net Connections
Board
Reference
Pin (J6)
Signal Name IO Standard Function
125 CONFIG0_1 CMOS Configuration mode channel 1, bit 0.
Internally pulled down.
127 CONFIG0_2 CMOS Configuration mode channel 2, bit 0.
Internally pulled down.
131 CONFIG1_1 CMOS Configuration mode channel 1, bit 1.
Internally pulled down.
133 CONFIG1_2 CMOS Configuration mode channel 2, bit 1.
Internally pulled down.
137 GPIO0_1 LVTTL Programmable general purpose I/O.
110 GPIO0_2 LVTTL Programmable general purpose I/O.
139 GPIO1_1 LVTTL Programmable general purpose I/O.
140 GPIO1_2 LVTTL Programmable general purpose I/O.
68 LASI1 CMOS Link Alarm Status Interrupt Channel 1.
128 LASI2 CMOS Link Alarm Status Interrupt Channel 2.
116 MDC2 CMOS Management Data Clock for single device
(default),
114 MDIO2 CMOS Management Data Clock channel 2 for dual
MDIO device.
41 MISO1 LVTTL Master Input/Slave Output Channel 1.
101 MISO2 LVTTL Master Input/Slave Output Channel 2.
78 MOD_ABS1 CMOS Module Absent Channel 1.
138 MOD_ABS2 CMOS Module Absent Channel 2.
43 MOSI1 LVTTL Master Output to Slave Input channel 1.
103 MOSI2 LVTTL Master Output to Slave Input channel 2.
121 NVMA1SEL LVTTL Non-volatile Memory Select
132 NVMPROT CMOS Non-volatile Memory Protect
61 OPINLVL LVTTL Optical Control Input Level.
59 OPOUTLVL LVTTL Optical Control Output Level.
42 OPRXLOS1 CMOS Optical Receiver Loss of Signal Channel 1.
102 OPRXLOS2 CMOS Optical Receiver Loss of Signal Channel 2.
44 OPTXFLT1 CMOS Optical Transmitter Fault Indicator Channel 1.
104 OPTXFLT2 CMOS Optical Transmitter Fault Indicator Channel 2.
62 PCDRLK1 LVTTL PMD CDR Lock Detect Channel 1.
122 PCDRLK2 LVTTL PMD CDR Lock Detect Channel 2.