LE910C1
Hardware User Guide
1VV0301298 Rev. 1.08 - 2017-11-14
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8.2.
HSIC Interface
The application processor exposes a High-Speed Inter-Chip (HSIC). HSIC eliminates the analog
transceiver from a USB interface for lower voltage operation and reduced power dissipation.
•
High-speed 480 Mbps (240 MHz DDR) USB transfers are 100% host driver compatible with
traditional USB cable connected topologies
•
Bidirectional data strobe signal (STROBE)
•
Bidirectional data signal (DATA)
•
No power consumption unless a transfer is in progress
Further details will be provided in a future release of this document.
8.3.
SGMII Interface (optional)
The SOC optionally includes an integrated Ethernet MAC with an SGMII interface, having the
following key features:
•
The SGMII interface can be used connect to an external Ethernet PHY, or an external switch.
•
When enabled, an additional network interface will be available to the Linux kernel’s
router.
8.3.1.
Ethernet Control interface
When using an external PHY for Ethernet connectivity, the LE910C1 also includes the control
interface for managing the external PHY
The table below lists the signals for controlling the external PHY
Table 24: Ethernet Control Interface Signals
PAD
Signal
I/O
Function
Type
COMMENT
C2
MAC_MDC O
MAC to PHY Clock
2.85V
C1
MAC_MDIO I/O MAC to PHY Data
2.85V
D1
ETH_RST_N O
Reset to Ethernet PHY
2.85V
G4
ETH_INT_N I
Interrupt from Ethernet PHY
1.8V
NOTE:
The Ethernet control interface is shared with USIM2 port!
When Ethernet PHY is used, USIM2 port cannot be used (and vice versa).
NOTE:
ETH_INT_N is a 1.8V input. It has an internal pull up to 1.8V inside the module thus it should be
connected to an open drain interrupt pin of the Ethernet PHY. In case the PHY does not support
1.8V I/O, proper level shifter needs to be used.
