GS2101M Low Power Wi-Fi Module Hardware User Guide
1VV0301395 Rev 3.0
Page
37
of
53
2017-11-13
Pin#
Pin Name
Internal
Pull
Resistor
mA
Mux3
Mux4
Mux5
Mux7
Comments
23
gpio36/sdio_dat0_d
out
d
4
sdio_data0 reserved i2c_data
spi0_dout
1
24
gpio37/sdio_dat1_int
d
4
sdio_data1
wuart_rx
uart1_rx
spi0_cs_n_10
25
NC
26
GND
27
gpio1/uart0_tx
d
4
uart0_tx
wuart_tx
pwm1
spi1_dout
1
28
gpio25/uart0_rts
d
12
uart0_rts
wuart_rts
spi1_cs_n_7
spi1_clk
29
gpio0_uart0_rx
d
4
uart0_rx
wuart_rx
pwm2
spi1_din
30
gpio24/uart0_cts
d
12
uart0_cts
wuart_cts
pwm0
spi1_cs_n_0
31
gpio31/pwm2
d
16
pwm2
spi1_dout
1
uart1_tx
wuart_tx
32
gpio30/pwm1
d
16
pwm1
spi1_din
uart1_rx
wuart_rx
33
GND
34
gpio28/i2c_data
d
12
i2c_data
spi1_clk
clk_hs_rc
spi1_cs_n_21
35
jtag_tck
36
jtag_tdo
37
jtag_tdi
38
jtag_tms
39
jtag_trst_n
40
GND
Tab. 6 GS2101M Pin MUX Description (Continued)
Note 1:
The SPI0_DOUT and SPI1_OUT signals do not disable their drive and
become Hi-Z when the associated chip select pin is high. This applies to all
pin MUX locations for the SPI_DOUT signals. If there are multiple write
only devices on the same SPI bus, then this is not an issue. This only
becomes an issue when there are other read/write devices on the same
SPI bus. The workaround is to add an external buffer chip, such as
74LVC1G125 between the SPI_DOUT pin and the SPI bus, with the
enable connected to the chip select signal.
Содержание GainSpan GS2101M
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