GS2011M Low Power Wi-Fi Module Hardware User Guide
1VV0301482 Rev. 5.0
Page
44
of
69
2018-01-10
34 VDDIO
VDDIO
Not Applicable
Analog port
All I/O voltage domain (can
be tied to VIN_3V3 or tied
to HOST I/O supply)
35
GPIO26/
UART1_CTS
VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/UART1Clear to Send
input (see Note 7)
36
GPIO27/
UART1_RTS
VDDIO
Pull-down (see Note 1
and Note 4)
4
Digital
Input/Output
GPIO/UART1 1 Request to
Send Output (see Note 7).
This pin is used for Program
Mode.
37
GPIO3/
UART1_RX
VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/UART1 Receive
Input
38
GPIO32/
SDIO_DAT2/
UART1_TX
VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/SDIO_DATA Bit
2/UART 1 Transmitter
Output
39
GPIO1/
UART0_TX
VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/UART0 Transmitter
Output.
40
GPIO25/
UART0_RTS
VDDIO
Pull-down (see Note 1)12
Digital
Input/Output
GPIO/UART0 Request to
Send Output (see Note 7).
This pin is used for Program
Select.
41
GPIO0/
UART0_RX
VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/UART0 Receive
Input
42
GPIO24/
UART0_CTS
VDDIO
Pull-down (see Note 1)12
Digital
Input/Output
GPIO/UART0 Clear to
Send Input (See Note 7)
43 GPIO31/PWM2
VDDIO
Pull-down (see Note 1)
16
(see Note 8)
Digital
Input/Output
GPIO/Pulse Width
Modulation Output 2
44 GPIO30/PWM1
VDDIO
Pull-down (see Note 1)
16
(see Note 8)
Digital
Input/Output
GPIO/Pulse Width
Modulation Output 1
45 GPIO29/I2C_CLK VDDIO
Pull-down (see Note 1)12
Digital
Input/Output
GPIO/I2C_CLK (see Note
4)
46
GPIO37/
SDIO_DAT1_INT
VDDIO
Pull-down (see Note 1
and Note 10)
4
Digital
Input/Output
GPIO/4-bit SDIO DATA bit
1/SDIO SPI Mode Interrupt
Table 7 GS2011Mxx Module Pin Signal Description (Continued)
Pins
Name
Voltage
Domain
Internal Bias after
Hardware Reset
Drive
Strength
(mA)
Signal State
Description
Содержание GainSpan GS2011M
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