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GS2011M Low Power Wi-Fi Module Hardware User Guide
1VV0301482 Rev. 5.0
Page
42
of
69
2018-01-10
3.1.1 GS2011Mxx Module Pins Description
describes the GS2011Mxx module pin signal description.
Table 7 GS2011Mxx Module Pin Signal Description
Pins
Name
Voltage
Domain
Internal Bias after
Hardware Reset
Drive
Strength
(mA)
Signal State
Description
1
GND
0V
Not Applicable
Analog port
Ground
2
JTAG_TCK
VDDIO
Pull-up (see Note 1)
Digital Input JTAG Test Clock
3
JTAG_TDO
VDDIO
Pull-down (see Note1)
Digital Output JTAG Test Data Out
4
JTAG_TDI
VDDIO
Pull-up (see Note 1)
Digital Input JTAG Test Data In
5
JTAG_TMS
VDDIO
Pull-up (see Note 1)
Digital Input JTAG Test Mode Select
6
JTAG_TRST_n
VDDIO
Pull-up (see Note 1)
Digital Input
JTAG Test Mode Reset
(Active Low)
7
RTC_IO_1
VRTC
Pull-down (see Note 1)1
RTC Digital
Input/Output
Embedded Real Time Clock
Input/Output 1
8
RTC_IO_0
VRTC
Pull-down (see Note 1)1
RTC Digital
Input/Output
Embedded Real Time Clock
Input/Output 0
9
VRTC
VRTC
Not Applicable
Analog port
Embedded Real Time Clock
Power Supply
10
DC_DC_CNTRL/
RTC_IO_4
VRTC
(see Note 1)
1
RTC Digital
Input/Output
VIN_3V3 Regulator
Control Output/RTC Digital
Input/Output
11 ADC_SAR_0
VIN_3V3 Not Applicable
Analog Input
General Analog to Digital
Converter, Successive
Approximation Register 0
12 ADC_SAR_1
VIN_3V3 Not Applicable
Analog Input
General Analog to Digital
Converter, Successive
Approximation Register 1
13
RTC_IO_2 (see
Note 2)
VRTC
Pull-down (see Note 1)1
RTC Digital
Input/Output
Embedded Real Time Clock
Input/Output 2
14 GPIO6/SPI1_DIN VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/Serial Peripheral
Interface 1 Bus Data Input
15
GPIO7 /
SPI1_DOUT
E-1
VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/Serial Peripheral
Interface 1 Bus Data Output
16 VOUT_1V8
VIN_3V3 Not Applicable
Analog port
Internal 1.8V V
OUT
(internally regulated)
17 GND
0V
Not Applicable
Analog port
Ground
18 GPIO5/SPI1_CLK VDDIO
Pull-down (see Note 1)4
Digital
Input/Output
GPIO/Serial Peripheral
Interface 1 Bus Clock
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