LE910Cx HW User Guide
1VV0301298 Rev. 33
Page 81 of 128
2021-06-29
Not Subject to NDA
Parameter
Comments
Min
Typ
Max
Unit
t(auxsync)
AUX_PCM__SYNC cycle time
-
125
-
µs
t(auxsynca)
AUX_PCM_SYNC asserted time
62.4
62.5
-
µs
t(auxsyncd)
AUX_PCM_SYNC de-asserted time
62.4
62.5
-
µs
t(auxclk)
AUX_PCM_CLK cycle time
-
7.8
-
µs
t(auxclkh)
AUX_PCM_CLK high time
3.8
3.9
-
µs
t(auxclkl)
AUX_PCM_CLK low time
3.8
3.9
-
µs
t(suauxsync)
AUX_PCM_SYNC setup time to
AUX_PCM_CLK rising
1.95
-
-
ns
t(hauxsync)
PCM_DIN hold time after
AUX_PCM_CLK rising
1.95
-
-
ns
t(suauxdin)
AUX_PCM_DIN setup time to
AUX_PCM_CLK falling
70
-
-
ns
t(hauxdin)
AUX_ PCM_DIN hold time after
AUX_PCM_CLK falling
20
-
-
ns
t(pauxdout)
Delay from AUX_PCM_CLK to
AUX_PCM_DOUT valid
-
-
50
ns
Table 35: AUX_PCM_CODEC Timing Parameters
8.6.1.3.
I2S Digital Audio Diagram