Tektronix WFM601, Руководство по обслуживанию

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Theory of Operation
3–8
WFM 601 - Service Manual
follower, sets the freerun frequency of the internal Voltage-Controlled Oscillator
(VCO).
Pins 9 through 18 (D0 – D9) are the single-ended, parallel ECL output of the
Deserializer. R35 and R36 are 1 k
pull-up resistor sets (7 resistors per set).
The DPR (Data Present) output of U3 (pin 35) drives the gate of Q2, a Field
Effect Transistor (FET). When the FET is turned on the drain, which outputs a
level to the Coprocessor, pulls down to 0V to indicate that serial data is being
received by the Deserializer. If the serial data stream is interrupted, Q2 turns off
and the drain goes high (No Serial).
The signal data bus to the Coprocessor is differential. U4 converts the single
ended ECL signal from the Deserializer to a differential ECL for input to the
Coprocessor circuitry.
The Deserializer, U3, outputs a differential reclocked serial digital video signal
from pins 3 and 4 (SX and SY). This differential signal is converted to single
ended Q4 and Q6 and limited. The output from Q7 (an emitter follower) can be
either 800 mV or reduced to 740 mV (some “first generation” serial equipment
requires a reduced level), to drive the 75
rear-panel Serial Out.
Diagram 3 Coprocessor
Data from the Deserializer is input to the Coprocessor as differential ECL. R5
-R16 are line terminating resistors. U1, U2, and U3 are ECL-to-TTL converters
outputting 10-bit, single ended TTL levels for the Coprocessor.
The serial clock is converted to TTL levels by U1, and output as a differential
signal to the DAC board (Diagram 4), where it is phase locked and regenerated
before returning to clock the Coprocessor. It returns to the Coprocessor circuit
board, as the internal clock, through J1 as 27 MHz and 27 MHz. Only the 27
MHz is used by the Coprocessor.
The No Signal from the Deserializer is the serial stream present indicator for the
Coprocessor. It is low when the serial data stream is present.
The Coprocessor relieves the Microprocessor of many line-by-line decisions as
well as determining when there are errors in the data stream and flagging gamut
errors.
The Coprocessor, U5, is clocked by the 27 MHz regenerated clock from Diagram
4. It provides 10–bit differential outputs (DACD0 - DACD9) to the DACs and
Signal Present Detector
ECL Line Driver
Coax Cable Driver
ECL to TTL Converter
Coprocessor