Tektronix TMS 440 SH-3 7708, Инструкция по эксплуатации

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Setting Up the Support
TMS 440 SH-3 7708 Microprocessor Support
2–7
CKIO
L_CAS~
Data
A ; C ; M ;
Row address
Address A25-A16
L_RAS~
Address A12 or A10
Row Address
Data
RD/WR~
L_BS~
Address A15-A0
Row Address
Column
Address
A ; D; C ; M ;
Column address
and Data
Row Address
Write
Command
Figure 2–5: SDRAM Write bus timing
PSRAM Access. PSRAM accesses are handled by DRAM/PSRAM/NORMAL
clocking option. In PSRAM Read, the Address, Data and Control signals are
logged-in every trailing CKIO edge when the DL_CASD~ AND DL_RASD~
qualifiers are low. When the DL_CASD~ is high at the next rising CKIO edge, it
is mastered. The DL_CASD~ for these cycles will go from low to high after a
trailing edge of CKIO before the rising edge of CKIO.
In PSRAM Write, the Address, Data and Control signals are logged-in every
trailing CKIO edge when the DL_WER~ AND DL_RASD~ qualifiers are low.
When the DL_WER~ is high at the next rising CKIO edge, it is mastered.
DL_WER~ for these cycles will go from low to high after a trailing edge of
CKIO before the rising edge of CKIO see Figure 2–6.