Tektronix TMS 440 SH-3 7708, Инструкция по эксплуатации

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Setting Up the Support
2–4
TMS 440 SH-3 7708 Microprocessor Support
DRAM Access. DRAM accesses are handled by DRAM/PSRAM/NORMAL or
A2–DRAM/A3–EDODRAM/NORMAL clocking options. The Address, Data,
and Control signals are logged-in every trailing CKIO edge when the
DL_CASD~ and DL_RASD~ qualifiers are low. When the DL_CASD~ is high
at the next rising CKIO edge it is mastered. The DL_CASD~ for these cycles
will go from low to high after a trailing edge of CKIO before the rising edge of
CKIO see Figure 2–2.
CKIO
L_BS~
Data
A ; D ; C
M ;
Address A25–A16
Address A15–A0
RD/WR~
Row address
Data
Row address
Column address
DL_RASD~
DL_CASD~
Figure 2–2: DRAM Access bus timing