Tektronix TMS 440 SH-3 7708, Инструкция по эксплуатации

Страница: 43 / 100

Setting Up the Support
TMS 440 SH-3 7708 Microprocessor Support
2–3
SRAM/ROM/PCMCIA Access. SRAM/ROM/PCMCIA accesses are handled by all
four clocking options. The Address, Data, and Control signals are logged-in
every trailing CKIO edge when the DL_WER~ qualifier is low, until the
DL_WER~ goes high. When the DL_WER~ is high at the next rising CKIO edge
it is mastered. The DL_WER~ for these cycles will go from low to high after a
trailing edge of CKIO and before the rising edge of CKIO see figure 2–1.
CKIO
L_BS~
Address A25–A0
RD~ (Asserted for Read )
Address
Data
Data
WEn~ (Asserted for Write)
DL_WER~(Asserted for
both Read and Write)
A ; D ; C
M ;
Figure 2–1: SRAM/ROM/PCMCIA Access bus timing