Tektronix TLA7XM, Руководство пользователя

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Specifications
1- 10
TLA721 Benchtop & TLA7XM Expansion Mainframe Service Manual
Table 1- 5: Backplane latencies (Cont.)
Characteristic Expansion mainframe Benchtop mainframe
DSO to LA inter-module System Trigger (TTLTRG7)
4
(DSO: Trigger all Modules
LA: Do Nothing)
--240 ns --204 ns
DSO to DSO inter-module System Trigger (TTLTRG7)
4
(DSO1: Trigger all Modules
DSO2: Wait for System Trigger)
50 ns 86 ns
DSO to LA inter-module ARM (TTLTRG2,4,5,6)
5
--192 ns + Clk --156 ns + Clk
DSO to DSO inter-module ARM (TTLTRG2,4,5,6) 59 ns 95 ns
DSO to LA inter-module via Signal 1, 2(ECLTRG0,1)
5, 6
(DSO: Trigger and set Signal 1
LA: Wait for Signal 1, then Trigger)
--179 ns + Clk --158 ns + Clk
DSO to LA inter-module via Signal 3, 4 (TTLTRG0,1)
5
(DSO: Trigger and set Signal 3
LA: Wait for Signal 3; then Trigger)
--184 ns + Clk --148 ns + Clk
1
SMPL represents the time from the event at the probe tip inputs to the next valid data sample of the LA module. In the
Normal Internal clock mode, this represents the delta time to the next sample clock. In the MagniVu Internal clock mode,
this represents 500 ps or less. In the External clock mode, this represents the time to the next master clock generated by
the setup of the clocking state machine, the system-under-test supplied clocks, and the qualification data.
2
All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with
signals measured in the wired-OR configuration.
3
All signal output latencies are validated to the rising edge of an active (true) high output.
4
In the Waveform window, triggers are always marked immediately except when delayed to the first sample. In the Listing
window, triggers are always marked on the next sample period following their occurrence.
5
“Clk” represents the time to the next master clock at the destination logic analyzer. In the asynchronous (or internal)
clock mode, this represents the delta time to the next sample clock beyond the minimum asynchronous rate of 4 ns. In
the synchronous (or external) clock mode, this represents the time to the next master clock generated by the setup of the
clocking state machine and the supplied system under test clocks and qualification data.
6
Signals 1 and 2 (ECLTRG0, 1) are limited to a “broadcast” mode of operation, where only one source is allowed to drive
the signal node at any one time. That single source may be utilized to drive any combination of destinations.