Tektronix TLA7XM, Руководство пользователя

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Specifications
1- 6
TLA721 Benchtop & TLA7XM Expansion Mainframe Service Manual
Table 1- 3: Backplane interface
Characteristic Description
Slots
Benchtop mainframe 13
Expansion mainframe 13
n
CLK10 Frequency 10 MHz
±
100 PPM
Relative Time Correlation Error
1,2
(Typical)
LA to LA “MagniVu” data 2 ns
LA to LA “normal” data utilizing an internal clock
4
1 LA sample -- 0.5 ns
LA to LA “normal” data utilizing an external clock 2 ns
LA “MagniVu” to DSO data
3
3 ns
LA to DSO “normal” data utilizing an internal clock
3,4
1 LA sample
±
2 ns
LA to DSO “normal” data utilizing an external clock
3,5
3 ns
DSO to DSO
3
3 ns
Enhanced monitor
Voltage readout +24 V, --24 V, +12 V, --12V, +5 V, --5.2 V, --2 V, +5 V
Standby
if
present, and +5 V
External
via RS232
Voltage readout accuracy ( Typical )
±
3% maximum
Current readout Readout of the present current on the +24 V, --24 V, +12 V,
--12 V, +5 V, --2 V, --5.2 V rails via RS232
Current readout accuracy ( Typical )
±
5% of maximum power supply I
mp
Rear panel connector levels
±
25 VDC maximum, 1 A maximum per pin
(Provides access for RS-232 host to enhanced monitor)
1
Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a “typical” number for the measure-
ment. Assumes standard accessory probes are utilized.
2
For time intervals longer than 1 s between modules, add 0.01% of the difference between the absolute time
measurements to the relative time correlation error to account for the inaccuracy of the CLK10 source.
3
The DSO module time correlation is measured at the maximum sample rate on one channel only.
4
Sample represents the time from the event to the next valid data sample at the probe tip of the LA. In the normal
Internal clock mode, this represents the delta time to the next sample clock
5
On this measurement, the DSO is measuring the CLK channel of the LA. If the DSO is measuring a data channel, the
time from when the data edge occurs until the clock edge occurs must be included.