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Performance Veri
fi
cation Procedures
Veri
fi
cation Procedure
Complete the following steps to complete this procedure. Record the results
on the Calibration Data Sheet.
1.
Press the RUN button and wait a few seconds to verify that it doesn’t trigger.
2.
Increase the delay of the DTG clock channel (starting from 0.000 ns), until
triggering begins to occur. Record this delay amount.
Note that the logic analyzer might trigger because of a glitch when you make
a delay change. If the data in the waveform window is correct (all data
transitioning at the same time and at the correct frequency), then ignore this
"false trigger" and start the logic analyzer again.
As an alternative, you may want to run the logic analyzer in continuous loop
mode if the DTG causes a false trigger on the logic analyzer each time you
change the delay. Then observe if the data is correct in the waveform window
and ignore any false triggers. Continue increasing the clock delay until the
waveform window displays data that was not acquired correctly. Record this
delay.
3.
Add 1.00 ns to the delay value that you recorded in step 2 and increase the
DTG clock delay to match this cumulative value. (For example, if you
measured 0.85 ns, increase the delay to 1.85 ns.)
4.
Press Run and wait a few seconds to verify that it doesn’t trigger. This veri
fi
es
that the setup and hold window is 1.00 ns or less, which is the guaranteed
speci
fi
cation for a single channel. If you are testing more than one channel,
you may need to add 1.50 ns to the value that you recorded in step 2 (1.5 ns
is the typical speci
fi
cation for multiple channels).
If you want to measure the actual setup and hold window size for your
application, slowly decrease the clock delay in steps (waiting a few seconds
between steps to verify that it doesn’t trigger), until the logic analyzer triggers.
Record this second value. The difference between this second value and the
value that you measured in step 2 is the measured setup and hold window size.
TLA5000 Series Product Speci
fi
cations & Performance Veri
fi
cation
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