Tektronix TLA 704, Руководство по обслуживанию

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Specifications
TLA 704 Color Portable Mainframe Service Manual
1–7
Table 1–5: Rear panel interface
Characteristic Description
LPT (Parallel Interface) Port 36-pin high-density connector supports standard Centronics mode,
Enhanced Parallel Port (EPP), or Microsoft high-speed mode (ECP)
Complies with IEEE P1284-C/D2 for bi-directional Parallel Peripheral
Interface for Personal Computers (draft) style 1284-C
COM (Serial Interface) Port 9-pin male sub-D connector to support RS-232 serial port.
SVGA Output Port 15-pin sub-D SVGA connector.
Type I and II PC Card Port Standard Type I and II PC-compatible PC card slot. Complies with
PCMCIA 2.1 and JEIDA 4.1
Type I, II, and III PC Card Port Standard Type I, II, and III PC-compatible PC card slot
System Trigger Input TTL-compatible inputs via rear-panel BNC connectors
Input Destination System trigger (TTLTRG7)
Input Levels V
IH
≥
2.0V; V
IL
≤
0.8V (TTL-compatible input)
Input Mode Falling edge sensitive, latched (active low)
Minimum Pulse Width 12 ns
Active Period Accepts system triggers during valid acquisition periods via real-time
gating; resets system trigger input latch between valid acquisition
periods.
Maximum Input Voltage 0 to +5V peak
External Signal Input TTL-compatible inputs via rear-panel BNC connectors
Input Destinations Signal 1, 2 (ECLTRG0, 1)
Signal 3, 4 (TTLTRG0, 1)
Input Levels V
IH
≥
2.0V; V
IL
≤
0.8V (TTL-compatible input)
Maximum Input Voltage 0 to +5V peak
Input Mode Active (true) low, level sensitive
Input Bandwidth Signal 1, 2: 50 MHz square wave minimum;
Signal 3, 4: 10 MHz square wave minimum.
Input bandwidth only applies to signals to the modules, not round-trip
signals into the external signal input and back out the external signal
output.
Active Period Accepts signals during valid acquisition periods via real-time gating