Tektronix Socket 7 TMS109A, Инструкция по эксплуатации

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Setting Up the Support
2–4
TMS 109A Socket 7 Microprocessor Support
Alternate Bus Master Cycles Excluded. Whenever the HLDA signal is high, no bus
cycles are logged in. Only bus cycles driven by the microprocessor (HLDA low)
will be logged in. Backoff cycles (caused by the BOFF# signal) are stored.
Alternate Bus Master Cycles Included.
All bus cycles, including alternate bus
master cycles and backoff cycles, are logged in.
When the HLDA signal is high, the microprocessor has given up the bus to an
alternate device. The design of the Socket 7 microprocessor system affects what
data will be logged in. The module only samples the data at the pins of the
microprocessor. To properly log in bus activity, any buffers between the
microprocessor and the alternate bus master must be enabled and pointing at the
Socket 7 microprocessor.
There are three possible Socket 7 microprocessor system designs and clocking
interactions when an alternate bus master has control of the bus. The three
different possibilities are listed below (in each case, the HLDA signal is logged
in as a high level):
H
If the alternate bus master drives the same control lines as the Socket 7
microprocessor, and the Socket 7 microprocessor sees these signals, the bus
activity is logged in like normal bus cycles except that the HLDA signal is
high.
H
If none of the control lines are driven or if the Socket 7 microprocessor can
not see them, the module will still clock in an alternate bus master cycle. The
information on the bus, one clock prior to the HLDA signal going low, is
logged in. If the ADS# signal goes low on the same clock when the HLDA
signal goes low, the address that gets logged in will be the next address, not
the address that occurred one clock before the HLDA signal went low.
H
If some of the Socket 7 microprocessor control lines are visible (but not all),
the module logs in the signals it determines are valid from the control signals
and logs in the remaining bus signals one clock cycle prior to the HLDA
signal going low. If the ADS# signal goes low on the same clock that the
HLDA signal goes low, the next address will be logged instead of the
previously saved address.
When the BOFF# signal goes low (active), a backoff cycle has been requested,
and the Socket 7 microprocessor gives up the bus on the next clock cycle. The
module aborts the bus cycle that it is currently logging in (the Socket 7
microprocessor will restart this cycle once the BOFF# signal goes high). A
backoff cycle will be logged in using one of the three interactions described for
the HLDA signal (except that the BOFF# signal is stored as a low-level signal in
each of the cases).