Tektronix PG 508, Инструкция по эксплуатации

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TM 11-6625-2980-14
THEORY OF OPERATION
Introduction
Refer to the block diagram and the schematics in the
foldout pages at the rear of this manual as well as the
following discussion to understand the operation of the
PG 508.
Input Circuitry
This circuitry processes the external trigger or gating
signal providing triggering waveforms for the period
circuit. The 50 n input impedance for this circuitry is
provided by R12, switched in or out by internal switch
S12. When R12 is out of the circuit, the input
impedance is 1 M n, obtained by R14 and R16. Diodes
CR16and CR17 are protective diodes. The proper
voltage at the drain of Q20 is set by VR20. The source
voltage of Q20 is set by VR22. Impedance
transformation, with no voltage shift, is obtained by
source follower Q20. Constant current for 020 is
supplied by Q22. A differential comparator is formed by
Q25 and Q26. This comparator compares the trigger or
gate input level with the level set by the front panel
TRIG/GATE control. Constant current for this
comparator is provided by Q30. Level control voltage for
the differential comparator is provided by operational
amplifier U40. The output, pin 6, swings over a range of
f3 V. The voltage at TP36 is the triggering level voltage,
as set by the TRIG/GATE LEVEL control. If the
triggering or gating voltage at the base of 025 is more
positive that TP36, then Q26 is conducting and 025 is
off. This places the collector of Q26 more positive than
the collector of Q25. When the gating or triggering
waveform level drops below TP36, Q25 conducts and
Q26 turns off.
This switching waveform is applied to the bases of
U60A and U60B, operating as a differential pair. The
collector of U60A drives U60C in a cascade mode of
operation. The collector of U60C drives the base of
U60D which, as an emitter follower, drives the input of
U70B. This gate operates as a dual input Schmitt trigger
shaper. When the emitter of U60D goes to about 4.2 V
above ground, pin 7 of U70B goes high. When the
emitter of U60D drops to about 3.8 V, pin 7 of U70B
drops to its low level. The inverting output terminal, pin
6, is always in the opposite state from pin 7. Positive
feedback for this portion of the Schmitt is provided by
R72. If the unit is manually triggered, pin 10 of U70B is
momentarily connected to +5 V. Pin 10 of U70B, along
with R75 and R76 now acts as a Schmitt shaper for the
manual trigger. This action holds the output, pin 7, high
and the inverting output, pin 6, low as long as the MAN
button is depressed.
When the plus slope is selected for triggering or
gating, +5 V is applied to pin 4 of U70A. This gate is
now inhibited and the signal passes through U70C. As
the outputs of U70A and C are connected together, a
high on either output overrides the low. Pin 13 of U70C
is low as long as the anodes of CR82 and CR84 are low,
which occurs when the logic circuitry has enabled the
input circuitry. When the control logic is set to disable
the input circuitry, the anodes of these diodes are raised
to +5 V which disables gates U70A and U70C.
Pin 12 of U70C now shifts between the high and low
state corresponding with the input gate or trigger. The
output from U70C, pin 14, is passed to the period
circuitry. A high at the output of U70C turns the period
circuitry off and a low starts the period generator.
TRIG'D/GATED Light Circuitry
Transistors Q100, 0102, 0110 and their associated
components compose the circuitry that operates the
front panel TRIG'D/GATE light emitting diode. The pair
Q100 and Q102 form a modified a stable multivibrator,
while Q110 operates as a voltage source. When the
output of U70A or U70C is high (period generator off) or
the logic circuitry has inhibited the input circuitry, the
base of 0Q100 is high. This causes the base of Q102 to
be low through R106. The collector of Q102 is now high
and the light emitting diode is off. When the base of
Q100 goes low, the base of Q102 goes high, the
collector goes low and the light emitting diode
illuminates. The light emitting diode circuitry follows the
triggering gate up to about a 5 Hz rate, i.e., about 100
ms on and 100 ms off. At faster gating frequencies,
C106 inhibits the changing states of this circuitry at
about the 5 Hz rate.
Triggered Mode
In the triggered mode of operation S200-2 is closed.
This places a high on pin 10 of U140B locking pin 7 high
and pin 6 low irrespective of the level on pin 11. This
disables the period generator. Pin 15 of U140C now
follows pin 4 of U140A in coincidence with the input
triggering signal. Pin 14 of U140C drives Q244 and pin
15 drives Q240. The output from the collector of 0240 is
in phase with the trigger or gate input signal providing
the trigger output, and the phase of the waveform at the
collector of Q244 is inverted.
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