Tektronix PG 508, Инструкция по эксплуатации

Страница: 119 / 182

TM 11-6625-2980-14
pulse is slow enough so that the D input of flip flop
U720A has not reached the high level when the pulse at
the clock terminal (pin 6) of flip flop U720A goes high
(leading portion of the next pulse driving the transition
circuitry) the 0 terminal, pin 3, of flip flop U720A goes
high. This high is connected to the set terminal, pin 12,
of U720B causing the 1 terminal of U720B to go high
illuminating the CONTROL ERROR light. The on time
and reset for this error indicating mode now proceeds as
previously described.
Level Control Multiplier
This circuitry provides independent top and bottom
level control of the output pulse by controlling the
amplitude and offset of the drive signal to the linear
output amplifier. Also included is circuitry to accomplish
the normal complement function and the preset
function. Control voltage clamps to ensure the output
amplifier is not over driven are also provided.
Amplitude control of the signal occurs in the analog
multiplier, U850. The pulse signal provides the X input,
and the level control voltages provide the Y input. The
X.Y product of these inputs is converted to a drive
current for the output amplifier.
Input and complement pulses from the variable
transition time generator are applied to the bases of
Q825 and 0840. These transistors form a differential
amplifier, supplied by constant current source U800B
and 0820. A positive-going signal at the base of Q825,
with the complementary (negative-going) signal at the
base of 0840 causes the signal current at pin 11 of the
multiplier to go negative and the signal current at pin 12
to go positive. When the pulse polarity reverses, at the
bases of Q825 and 0840, the signal current also
reverses polarity at pins 11 and 12. The difference
between the currents at pins 11 and 12 corresponds to
the X signal input for the multiplier.
The total current flowing from pins 2 and 3 of U850 is
essentially equal to the current required by the constant
current source, U895A and Q900. However, the
difference in currents between these pins corresponds to
the Y input signal for the multiplier.
The amplitude difference of these currents is
controlled by U895B. This is a dc differential amplifier
which amplifies the difference between the high & low
level control voltages to produce the Y input signal.
Gain adjustment for the Y input signal is provided by
R885.
The high and low level control voltages are
determined by their respective front panel controls,
R770B and R770A. If the preset function is selected, the
preset high and preset low potentiometers, R775 and
R785, provide the control voltages. These voltages are
buffered by unity gain amplifiers U780A and U780B.
Both control voltages range
between 0 and +5.2 V. When the control voltages are
equal, the Y input is zero and the multiplier signal output
(X.Y) equals zero. A difference of +2.6 V between the
high and low level control voltages corresponds to
maximum output amplitude from the pulse generator.
The normal complement switch inverts the level
control voltage inputs to differential amplifier U895B.
However, since the difference between the voltages is
unchanged, the control voltage input signal has constant
amplitude, but reverses polarity. This complements the
pulse generator output. The normal complement
balance adjustment, R910, ensures that the Y multiplier
input responds equally to changes in either the high or
low level control voltages.
The signal current at pins 5 and 6 of U850 is the pulse
signal. Since 0845, in conjunction with U800B, provides
a constant current sink, the current through R954, from
the emitter of common base stage Q954, also contains
signal current variations. The current driver for the
output amplifier is Q954. The signal currents into pins 8
and 9 of U850 also contain the pulse signal. However
constant current sink R847, and common base stage
0950 are included only as a balancing thermal load for
the multiplier.
To obtain independent control of the output pulse high
and low levels, the control voltages are averaged by
resistor network R914, R915, R918 and R920. High and
Low tracking potentiometers, R915 and R920, are
adjustable to provide minimum interaction between
pulse levels. The dc voltage from this network, along
with the voltage from the offset adjustment R925, is
summed and inverted by U930A. U930B proves further
gain and level shifting and, in conjunction with 0945,
serves as a level controlled offset generator. A dc
current source to the collector of Q954 is provided by
Q945. The collector of Q954 is the virtual ground input
to the output amplifier.
When the high and low level control potentiometers
are both at midrange (+2.6 V zero output) 0945 sources
all the quiescent bias current required by 0954, which is
approximately 15 mA. Therefore, there is no current
drive to the output amplifier through R975 or Rl1055. If
the high level control is turned fully cw (maximum
output), the low level control voltage remains at +2.6 V.
The high level control voltage increases to +5.2 V. This
causes the voltage output of U930A to decrease,
causing the offset generator U930B and 0945 to source
approximately 20 mA. This is an increase of 5 mA. This
difference in control voltage settings also causes
maximum difference in the control voltage input signal
to the multiplier. This action also causes 10 mA peak to
peak signal current variations in the collector current of
Q954. Since the signal current
2-5