Tektronix P6910, Инструкция по эксплуатации

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Reference
Clock and quali fi ers
Use the clock and quali fi er probe connections from the SUT to de fi ne how the
logic analyzer stores data.
Every logic analyzer has some-special purpose input channels. Inputs designated
as clocks can cause the logic analyzer to store data. Quali
fi er channels can be
logically AND’ed and OR’ed with clocks to further de fi ne when to latch data
from the SUT. Routing the appropriate signals from the design to these inputs
ensures that the logic analyzer can acquire data correctly. Unused clocks can be
used as quali
fi er signals.
Depending on the channel width, each logic analyzer will have a different set of
clock and quali
fi er channels. The following table shows the availability of the
clock and quali fi er channels.
Table 1: Logic analyzer clock and quali fi er availability
Clock inputs Quali fi er inputs Logic analyzer width
CLK:0 CLK:1 CLK:2 CLK:3 QUAL:0 QUAL:1 QUAL:2 QUAL:3
34-channel
68-channel
102-channel
136-channel
All clock and quali fi er channels are stored. The logic analyzer always stores the
logic state of these channels every time it latches data.
Since clock and quali fi er channels are stored in memory there is no need to
double-probe these signals for timing analysis. When switching from state to
timing analysis modes, all of the clock and quali
fi er signals will be visible. This
also allows you to route regular signals, those not needed for clocking, to these
channels when they are not being used for their special purpose.
It is a good practice to take advantage of these channels to increase your options
for when you will latch data. Routing several of your design's clocks and strobes
to the logic analyzer clock inputs will provide you with a greater
fl exibility in the
logic analyzer clocking setup menus.
As an example, look at a processor with a master clock, a data strobe, and an
address strobe. Routing all three of these signals to the logic analyzer clock inputs
will enable you to latch data on the processor master clock, only when data is
strobed, or only when address is strobed. Some forethought in signal routing can
greatly expand the ways to latch and analyze data.
P6910 General Purpose Probe Instruction Manual 17